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author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2012-10-30 08:20:56 +0100 |
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committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2012-10-30 08:20:56 +0100 |
commit | 53279f36dccffc26ff536003fd6bb97cc21c3b82 (patch) | |
tree | 9d16e497c0e4158c7c054c479bd0e9ff0388d7bb /Documentation/devicetree/bindings/arm/msm/timer.txt | |
parent | Input: qt2160 - fix qt2160_write() implementation (diff) | |
parent | Linux 3.7-rc3 (diff) | |
download | linux-53279f36dccffc26ff536003fd6bb97cc21c3b82.tar.xz linux-53279f36dccffc26ff536003fd6bb97cc21c3b82.zip |
Merge tag 'v3.7-rc3' into next to sync up with recent USB and MFD changes
Diffstat (limited to 'Documentation/devicetree/bindings/arm/msm/timer.txt')
-rw-r--r-- | Documentation/devicetree/bindings/arm/msm/timer.txt | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/msm/timer.txt b/Documentation/devicetree/bindings/arm/msm/timer.txt new file mode 100644 index 000000000000..8c5907b9cae8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/timer.txt @@ -0,0 +1,38 @@ +* MSM Timer + +Properties: + +- compatible : Should at least contain "qcom,msm-timer". More specific + properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general + purpose timer and a debug timer respectively. + +- interrupts : Interrupt indicating a match event. + +- reg : Specifies the base address of the timer registers. The second region + specifies an optional register used to configure the clock divider. + +- clock-frequency : The frequency of the timer in Hz. + +Optional: + +- cpu-offset : per-cpu offset used when the timer is accessed without the + CPU remapping facilities. The offset is cpu-offset * cpu-nr. + +Example: + + timer@200a004 { + compatible = "qcom,msm-gpt", "qcom,msm-timer"; + interrupts = <1 2 0x301>; + reg = <0x0200a004 0x10>; + clock-frequency = <32768>; + cpu-offset = <0x40000>; + }; + + timer@200a024 { + compatible = "qcom,msm-dgt", "qcom,msm-timer"; + interrupts = <1 3 0x301>; + reg = <0x0200a024 0x10>, + <0x0200a034 0x4>; + clock-frequency = <6750000>; + cpu-offset = <0x40000>; + }; |