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authorIngo Molnar <mingo@kernel.org>2015-09-13 10:01:24 +0200
committerIngo Molnar <mingo@kernel.org>2015-09-13 10:01:24 +0200
commitc7ef92cea98bc468bbc8e67b6e49d7365dc69482 (patch)
tree1ed0118f697d72103eaf8fa53bd373be7a1c91ff /Documentation/devicetree/bindings/arm/pmu.txt
parentlocking/qspinlock/x86: Only emit the test-and-set fallback when building gues... (diff)
parentLinux 4.3-rc1 (diff)
downloadlinux-c7ef92cea98bc468bbc8e67b6e49d7365dc69482.tar.xz
linux-c7ef92cea98bc468bbc8e67b6e49d7365dc69482.zip
Merge tag 'v4.3-rc1' into locking/core, to refresh the tree
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/arm/pmu.txt')
-rw-r--r--Documentation/devicetree/bindings/arm/pmu.txt12
1 files changed, 9 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt
index 3b5f5d1088c6..435251fa9ce0 100644
--- a/Documentation/devicetree/bindings/arm/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/pmu.txt
@@ -26,13 +26,19 @@ Required properties:
Optional properties:
-- interrupt-affinity : Valid only when using SPIs, specifies a list of phandles
- to CPU nodes corresponding directly to the affinity of
+- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU
+ nodes corresponding directly to the affinity of
the SPIs listed in the interrupts property.
- This property should be present when there is more than
+ When using a PPI, specifies a list of phandles to CPU
+ nodes corresponding to the set of CPUs which have
+ a PMU of this type signalling the PPI listed in the
+ interrupts property.
+
+ This property should be present when there is more than
a single SPI.
+
- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
events.