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authorRob Herring <robh@kernel.org>2018-04-25 21:24:59 +0200
committerRob Herring <robh@kernel.org>2018-04-27 23:56:47 +0200
commit2359ccddc1c3f4752f43cc19b3db189710b15791 (patch)
tree176ed8de6384351f7a901f6109d121bac41d0e24 /Documentation/devicetree/bindings/c6x
parentdt-bindings: thermal: rcar-gen3-thermal: update register size in example (diff)
downloadlinux-2359ccddc1c3f4752f43cc19b3db189710b15791.tar.xz
linux-2359ccddc1c3f4752f43cc19b3db189710b15791.zip
dt-bindings: move various timer bindings to timer/ directory
Bindings are supposed to be organized by device class/function. Move bindings for various timers to timer/ binding directory. Cc: Linus Walleij <linus.walleij@linaro.org> Acked-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/c6x')
-rw-r--r--Documentation/devicetree/bindings/c6x/timer64.txt26
1 files changed, 0 insertions, 26 deletions
diff --git a/Documentation/devicetree/bindings/c6x/timer64.txt b/Documentation/devicetree/bindings/c6x/timer64.txt
deleted file mode 100644
index 95911fe70224..000000000000
--- a/Documentation/devicetree/bindings/c6x/timer64.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Timer64
--------
-
-The timer64 node describes C6X event timers.
-
-Required properties:
-
-- compatible: must be "ti,c64x+timer64"
-- reg: base address and size of register region
-- interrupt-parent: interrupt controller
-- interrupts: interrupt id
-
-Optional properties:
-
-- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface.
-
-- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer.
-
-Example:
- timer0: timer@25e0000 {
- compatible = "ti,c64x+timer64";
- ti,core-mask = < 0x01 >;
- reg = <0x25e0000 0x40>;
- interrupt-parent = <&megamod_pic>;
- interrupts = < 16 >;
- };