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| author | Ingo Molnar <mingo@kernel.org> | 2015-02-28 08:03:10 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2015-02-28 08:03:10 +0100 |
| commit | 5838d18955b52467f4b30486e62a31727b39998d (patch) | |
| tree | 8aeb8412156bab93a6b39f2de4a8d6c912ddb31a /Documentation/devicetree/bindings/clock/qoriq-clock.txt | |
| parent | x86/platform/intel-mid: Fix trivial printk message typo in intel_mid_arch_set... (diff) | |
| parent | Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/... (diff) | |
| download | linux-5838d18955b52467f4b30486e62a31727b39998d.tar.xz linux-5838d18955b52467f4b30486e62a31727b39998d.zip | |
Merge branch 'linus' into x86/urgent, to merge dependent patch
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/qoriq-clock.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/qoriq-clock.txt | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index 266ff9d23229..df4a259a6898 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -1,6 +1,6 @@ -* Clock Block on Freescale CoreNet Platforms +* Clock Block on Freescale QorIQ Platforms -Freescale CoreNet chips take primary clocking input from the external +Freescale qoriq chips take primary clocking input from the external SYSCLK signal. The SYSCLK input (frequency) is multiplied using multiple phase locked loops (PLL) to create a variety of frequencies which can then be passed to a variety of internal logic, including @@ -29,6 +29,7 @@ Required properties: * "fsl,t4240-clockgen" * "fsl,b4420-clockgen" * "fsl,b4860-clockgen" + * "fsl,ls1021a-clockgen" Chassis clock strings include: * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks |