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author | Johannes Berg <johannes.berg@intel.com> | 2015-06-10 12:44:58 +0200 |
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committer | Johannes Berg <johannes.berg@intel.com> | 2015-06-10 12:45:09 +0200 |
commit | 206c59d1d7d42bcafc1d7f1e476e87e4427e2345 (patch) | |
tree | a2f99470bd0fe43f5cf57812fca969bb3ca3c451 /Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt | |
parent | mac80211: Fix a case of incorrect metric used when forwarding a PREQ (diff) | |
parent | Merge tag 'batman-adv-for-davem' of git://git.open-mesh.org/linux-merge (diff) | |
download | linux-206c59d1d7d42bcafc1d7f1e476e87e4427e2345.tar.xz linux-206c59d1d7d42bcafc1d7f1e476e87e4427e2345.zip |
Merge remote-tracking branch 'net-next/master' into mac80211-next
Merge back net-next to get wireless driver changes (from Kalle)
to be able to create the API change across all trees properly.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt')
-rw-r--r-- | Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt new file mode 100644 index 000000000000..2f3747fdcf1c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt @@ -0,0 +1,25 @@ +* Renesas R8A7778 Clock Pulse Generator (CPG) + +The CPG generates core clocks for the R8A7778. It includes two PLLs and +several fixed ratio dividers + +Required Properties: + + - compatible: Must be "renesas,r8a7778-cpg-clocks" + - reg: Base address and length of the memory resource used by the CPG + - #clock-cells: Must be 1 + - clock-output-names: The names of the clocks. Supported clocks are + "plla", "pllb", "b", "out", "p", "s", and "s1". + + +Example +------- + + cpg_clocks: cpg_clocks@ffc80000 { + compatible = "renesas,r8a7778-cpg-clocks"; + reg = <0xffc80000 0x80>; + #clock-cells = <1>; + clocks = <&extal_clk>; + clock-output-names = "plla", "pllb", "b", + "out", "p", "s", "s1"; + }; |