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author | Rafał Miłecki <rafal@milecki.pl> | 2023-11-19 22:24:16 +0100 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2023-12-18 00:21:19 +0100 |
commit | 94b0f301f6ee92f79a2fe2c655dfdbdfe2aec536 (patch) | |
tree | 4a56166aa3d8bd76ef538a084675ac369fc4b1cf /Documentation/devicetree/bindings/clock | |
parent | dt-bindings: Remove alt_ref from versal (diff) | |
download | linux-94b0f301f6ee92f79a2fe2c655dfdbdfe2aec536.tar.xz linux-94b0f301f6ee92f79a2fe2c655dfdbdfe2aec536.zip |
dt-bindings: arm: mediatek: move ethsys controller & convert to DT schema
DT schema helps validating DTS files. Binding was moved to clock/ as
this hardware is a clock provider. Example required a small fix for
"reg" value (1 address cell + 1 size cell).
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20231119212416.2682-1-zajec5@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
-rw-r--r-- | Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml new file mode 100644 index 000000000000..94d42c864777 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek ethsys controller + +description: + The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +maintainers: + - James Liao <jamesjj.liao@mediatek.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-ethsys + - mediatek,mt7622-ethsys + - mediatek,mt7629-ethsys + - mediatek,mt7981-ethsys + - mediatek,mt7986-ethsys + - const: syscon + - items: + - const: mediatek,mt7623-ethsys + - const: mediatek,mt2701-ethsys + - const: syscon + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@1b000000 { + compatible = "mediatek,mt2701-ethsys", "syscon"; + reg = <0x1b000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; |