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| author | Biju Das <biju.das@bp.renesas.com> | 2018-09-11 12:12:47 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-09-19 16:36:53 +0200 |
| commit | bbd71915ee9c56cc585c76b4b3aee791152ffbff (patch) | |
| tree | e5340bc10c4eefa812493fb47e57ed3b3cc138c2 /Documentation/devicetree/bindings/clock | |
| parent | dt-bindings: clock: renesas: Convert to SPDX identifiers (diff) | |
| download | linux-bbd71915ee9c56cc585c76b4b3aee791152ffbff.tar.xz linux-bbd71915ee9c56cc585c76b4b3aee791152ffbff.zip | |
dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding
Add binding documentation for the RZ/G1N (R8A7744) Clock Pulse
Generator driver.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt index 5e46e6be789b..629dd4f8ddac 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt @@ -15,6 +15,7 @@ Required Properties: - compatible: Must be one of: - "renesas,r7s9210-cpg-mssr" for the r7s9210 SoC (RZ/A2) - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M) + - "renesas,r8a7744-cpg-mssr" for the r8a7744 SoC (RZ/G1N) - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E) - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C) - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M) @@ -37,12 +38,12 @@ Required Properties: - clocks: References to external parent clocks, one entry for each entry in clock-names - clock-names: List of external parent clock names. Valid names are: - - "extal" (r7s9210, r8a7743, r8a7745, r8a77470, r8a774a1, r8a7790, - r8a7791, r8a7792, r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, - r8a77970, r8a77980, r8a77990, r8a77995) + - "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1, + r8a7790, r8a7791, r8a7792, r8a7793, r8a7794, r8a7795, r8a7796, + r8a77965, r8a77970, r8a77980, r8a77990, r8a77995) - "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980) - - "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793, - r8a7794) + - "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791, + r8a7793, r8a7794) - #clock-cells: Must be 2 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" |