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authorJoseph Lo <josephl@nvidia.com>2019-01-04 04:06:46 +0100
committerThierry Reding <treding@nvidia.com>2019-02-06 14:27:52 +0100
commitc79a3ccb191809c356044564859c275fba8e5b0f (patch)
tree29d750a1dff7975daf9beb861a7395546c19bd14 /Documentation/devicetree/bindings/cpufreq
parentdt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties (diff)
downloadlinux-c79a3ccb191809c356044564859c275fba8e5b0f.tar.xz
linux-c79a3ccb191809c356044564859c275fba8e5b0f.zip
dt-bindings: cpufreq: tegra124: remove cpu_lp clock from required properties
The cpu_lp clock property is only needed when the CPUfreq driver supports CPU cluster switching. But it was not a design for this driver and it didn't handle that as well. So removing this property. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'Documentation/devicetree/bindings/cpufreq')
-rw-r--r--Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt4
1 files changed, 1 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt
index 031545a29caf..03196d5ea515 100644
--- a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt
+++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt
@@ -9,7 +9,6 @@ Required properties:
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- cpu_g: Clock mux for the fast CPU cluster.
- - cpu_lp: Clock mux for the low-power CPU cluster.
- pll_x: Fast PLL clocksource.
- pll_p: Auxiliary PLL used during fast PLL rate changes.
- dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
@@ -30,11 +29,10 @@ cpus {
reg = <0>;
clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
- <&tegra_car TEGRA124_CLK_CCLK_LP>,
<&tegra_car TEGRA124_CLK_PLL_X>,
<&tegra_car TEGRA124_CLK_PLL_P>,
<&dfll>;
- clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
+ clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
clock-latency = <300000>;
};