summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/display
diff options
context:
space:
mode:
authorMaxime Ripard <maxime.ripard@free-electrons.com>2016-06-09 14:01:58 +0200
committerMaxime Ripard <maxime.ripard@free-electrons.com>2016-09-08 09:31:13 +0200
commitcd8fff504d636b28abad652b0ae45f8b54ab0cc9 (patch)
tree81967630260a8e89e6a342b73fa5c315fe3cabb5 /Documentation/devicetree/bindings/display
parentdrm/sun4i: backend: Handle the SAT (diff)
downloadlinux-cd8fff504d636b28abad652b0ae45f8b54ab0cc9.tar.xz
linux-cd8fff504d636b28abad652b0ae45f8b54ab0cc9.zip
drm/sun4i: Add a DRC driver
The A33 pipeline also has a component called DRC. Even though its exact features and programming model is not known (or documented), it needs to be clocked for the pipeline to carry the video signal all the way. Add a minimal driver for it that just claim the needed resources for the pipeline to operate properly. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Peter Korsgaard <peter@korsgaard.com>
Diffstat (limited to 'Documentation/devicetree/bindings/display')
-rw-r--r--Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt24
1 files changed, 24 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index abe9e9d8b785..b95696d748c7 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -53,6 +53,30 @@ Required properties:
On the A13, there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
+DRC
+---
+
+The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
+(A31, A23, A33), allows to dynamically adjust pixel
+brightness/contrast based on histogram measurements for LCD content
+adaptive backlight control.
+
+
+Required properties:
+ - compatible: value must be one of:
+ * allwinner,sun8i-a33-drc
+ - reg: base address and size of the memory-mapped region.
+ - interrupts: interrupt associated to this IP
+ - clocks: phandles to the clocks feeding the DRC
+ * ahb: the DRC interface clock
+ * mod: the DRC module clock
+ * ram: the DRC DRAM clock
+ - clock-names: the clock names mentioned above
+ - resets: phandles to the reset line driving the DRC
+
+- ports: A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
+ first port should be the input endpoints, the second one the outputs
Display Engine Backend
----------------------