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| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2016-03-18 15:24:41 +0100 |
|---|---|---|
| committer | Vinod Koul <vinod.koul@intel.com> | 2016-04-13 18:06:09 +0200 |
| commit | c422025c185fb2bb28df65b1bbed7953480c7f87 (patch) | |
| tree | d3065d734e40581f4c38b53827c99f31ae901027 /Documentation/devicetree/bindings/dma/snps-dma.txt | |
| parent | dmaengine: dw: fix master selection (diff) | |
| download | linux-c422025c185fb2bb28df65b1bbed7953480c7f87.tar.xz linux-c422025c185fb2bb28df65b1bbed7953480c7f87.zip | |
dmaengine: dw: rename masters to reflect actual topology
The source and destination masters are reflecting buses or their layers to
where the different devices can be connected. The patch changes the master
names to reflect which one is related to which independently on the transfer
direction.
The outcome of the change is that the memory data width is now always limited
by a data width of the master which is dedicated to communicate to memory.
The patch will not break anything since all current users have the same data
width for all masters. Though it would be nice to revisit avr32 platforms to
check what is the actual hardware topology in use there. It seems that it has
one bus and two masters on it as stated by Table 8-2, that's why everything
works independently on the master in use. The purpose of the sequential patch
is to fix the driver for configuration of more than one bus.
The change is done in the assumption that src_master and dst_master are
reflecting a connection to the memory and peripheral correspondently on avr32
and otherwise on the rest.
Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'Documentation/devicetree/bindings/dma/snps-dma.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/dma/snps-dma.txt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt index c261598164a7..c99c1ffac199 100644 --- a/Documentation/devicetree/bindings/dma/snps-dma.txt +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt @@ -47,8 +47,8 @@ The four cells in order are: 1. A phandle pointing to the DMA controller 2. The DMA request line number -3. Source master for transfers on allocated channel -4. Destination master for transfers on allocated channel +3. Memory master for transfers on allocated channel +4. Peripheral master for transfers on allocated channel Example: |