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| author | Bjorn Andersson <bjorn.andersson@linaro.org> | 2017-08-15 00:46:18 +0200 |
|---|---|---|
| committer | Andy Gross <andy.gross@linaro.org> | 2017-10-12 06:48:27 +0200 |
| commit | 8c1b7dc9ba2294c6dbd1870a3d2e534bfda3047a (patch) | |
| tree | 8d9823b880adb03cdf422d6773c720b79c6233e5 /Documentation/devicetree/bindings/firmware | |
| parent | firmware: qcom: scm: Expose secure IO service (diff) | |
| download | linux-8c1b7dc9ba2294c6dbd1870a3d2e534bfda3047a.tar.xz linux-8c1b7dc9ba2294c6dbd1870a3d2e534bfda3047a.zip | |
firmware: qcom: scm: Expose download-mode control
In order to aid post-mortem debugging the Qualcomm platforms provide a
"memory download mode", where the boot loader will provide an interface
for custom tools to "download" the content of RAM to a host machine.
The mode is triggered by writing a magic value somewhere in RAM, that is
read in the boot code path after a warm-restart. Two mechanism for
setting this magic value are supported in modern platforms; a direct SCM
call to enable the mode or through a secure io write of a magic value.
In order for a normal reboot not to trigger "download mode" the magic
must be cleared during a clean reboot.
Download mode has to be enabled by including qcom_scm.download_mode=1 on
the command line.
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/firmware')
| -rw-r--r-- | Documentation/devicetree/bindings/firmware/qcom,scm.txt | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt index 20f26fbce875..7b40054be0d8 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -18,6 +18,8 @@ Required properties: * Core, iface, and bus clocks required for "qcom,scm" - clock-names: Must contain "core" for the core clock, "iface" for the interface clock and "bus" for the bus clock per the requirements of the compatible. +- qcom,dload-mode: phandle to the TCSR hardware block and offset of the + download mode control register (optional) Example for MSM8916: |