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authorHuang Rui <ray.huang@amd.com>2014-10-28 12:54:35 +0100
committerFelipe Balbi <balbi@ti.com>2014-11-03 17:03:38 +0100
commit2164a476205ccc62c5874f95f3504b657fff5c04 (patch)
tree6ddb9220c0e77851c50891f4cbbaa046a26e973a /Documentation/devicetree/bindings/input/twl4030-pwrbutton.txt
parentusb: dwc3: add rx_detect to polling lfps quirk (diff)
downloadlinux-2164a476205ccc62c5874f95f3504b657fff5c04.tar.xz
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usb: dwc3: set SUSPHY bit for all cores
It is recommended to set USB3 and USB2 SUSPHY bits to '1' after the core initialization is completed above the dwc3 revision 1.94a. Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
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