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author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2016-08-05 16:55:18 +0200 |
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committer | Jason Cooper <jason@lakedaemon.net> | 2016-08-16 15:59:04 +0200 |
commit | 33a6c324a7266462f933ab25a92383c882e4b4f1 (patch) | |
tree | 40031ccbe38e5ccae4744afab1b89d8d4f630df6 /Documentation/devicetree/bindings/interrupt-controller | |
parent | Linux 4.8-rc1 (diff) | |
download | linux-33a6c324a7266462f933ab25a92383c882e4b4f1.tar.xz linux-33a6c324a7266462f933ab25a92383c882e4b4f1.zip |
dt-bindings: interrupt-controller: add DT binding for Marvell 7K/8K PIC
This commit adds the Device Tree binding description for the PIC
interrupt controller available in the ARM64 Marvell Armada 7K/8K SoCs.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/1470408921-447-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'Documentation/devicetree/bindings/interrupt-controller')
-rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt new file mode 100644 index 000000000000..86a7b4cd03f5 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt @@ -0,0 +1,25 @@ +Marvell Armada 7K/8K PIC Interrupt controller +--------------------------------------------- + +This is the Device Tree binding for the PIC, a secondary interrupt +controller available on the Marvell Armada 7K/8K ARM64 SoCs, and +typically connected to the GIC as the primary interrupt controller. + +Required properties: +- compatible: should be "marvell,armada-8k-pic" +- interrupt-controller: identifies the node as an interrupt controller +- #interrupt-cells: the number of cells to define interrupts on this + controller. Should be 1 +- reg: the register area for the PIC interrupt controller +- interrupts: the interrupt to the primary interrupt controller, + typically the GIC + +Example: + + pic: interrupt-controller@3f0100 { + compatible = "marvell,armada-8k-pic"; + reg = <0x3f0100 0x10>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; + }; |