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authorGeert Uytterhoeven <geert+renesas@glider.be>2019-10-24 15:14:23 +0200
committerMauro Carvalho Chehab <mchehab@kernel.org>2019-11-05 13:02:32 +0100
commitd619a95693acbab64e0cdc76ddee5e214c4363f3 (patch)
tree025125d47ef7f1d60dd281d2eec5a84d26ebd4cb /Documentation/devicetree/bindings/media
parentmedia: fdp1: Fix R-Car M3-N naming in debug message (diff)
downloadlinux-d619a95693acbab64e0cdc76ddee5e214c4363f3.tar.xz
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media: dt-bindings: rcar_vin: Document RZ/G1 per-board settings
The R-Car Gen2 per-board settings apply to RZ/G1, too. Fixes: 1d14a5eaa156b0b3 ("media: dt-bindings: media: rcar_vin: add device tree support for r8a774[35]") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/media')
-rw-r--r--Documentation/devicetree/bindings/media/renesas,vin.txt4
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/media/renesas,vin.txt b/Documentation/devicetree/bindings/media/renesas,vin.txt
index 103faadd5d4e..e30b0d4eefdd 100644
--- a/Documentation/devicetree/bindings/media/renesas,vin.txt
+++ b/Documentation/devicetree/bindings/media/renesas,vin.txt
@@ -44,7 +44,7 @@ on Gen3 and RZ/G2 platforms to a CSI-2 receiver.
Additionally, an alias named vinX will need to be created to specify
which video input device this is.
-The per-board settings Gen2 platforms:
+The per-board settings for Gen2 and RZ/G1 platforms:
- port - sub-node describing a single endpoint connected to the VIN
from external SoC pins as described in video-interfaces.txt[1].
@@ -64,7 +64,7 @@ The per-board settings Gen2 platforms:
- data-enable-active: polarity of CLKENB signal, see [1] for
description. Default is active high.
-The per-board settings Gen3 and RZ/G2 platforms:
+The per-board settings for Gen3 and RZ/G2 platforms:
Gen3 and RZ/G2 platforms can support both a single connected parallel input
source from external SoC pins (port@0) and/or multiple parallel input sources