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author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-07-09 18:17:59 +0200 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-07-09 18:17:59 +0200 |
commit | c6b6cebbc597aaf7d941f781b5fc114c58cc3352 (patch) | |
tree | a99ad03f0f53552338db140f34c325e47c6b54e4 /Documentation/devicetree/bindings/mfd | |
parent | Merge tag 'regulator-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/b... (diff) | |
parent | Merge remote-tracking branch 'spi/topic/pump-rt' into spi-next (diff) | |
download | linux-c6b6cebbc597aaf7d941f781b5fc114c58cc3352.tar.xz linux-c6b6cebbc597aaf7d941f781b5fc114c58cc3352.zip |
Merge tag 'spi-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown:
"For the most part this is a quiet release for SPI, though there's
several of the more widely used drivers that have had some fairly
substantial development done on them, mainly improving performance and
adding support for some more obscure use cases.
Summary:
- Support for configuring a minimum time for chip select to be
deasserted between transfers from Martin Sperl.
- A rework of the ACPI device instantiation code from Ard Biesheuvel.
- Fairly substantial development on the AT91 USART, BCM2835 and
Tegra114 drivers.
- New driver for Socionext SynQuacer"
* tag 'spi-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (58 commits)
spi: pxa2xx: Add support for Intel Elkhart Lake
spi: atmel-quadspi: fix resume call
spi: atmel-quadspi: void return type for atmel_qspi_init()
spi: pxa2xx: Set minimum transfer speed
spi: stm32-qspi: remove signal sensitive on completion
dt-bindings: spi: stm32-qspi: add dma properties
spi: uniphier: fix zero-length transfer
spi: uniphier: fix timeout error
spi/acpi: avoid spurious matches during slave enumeration
spi: spi-stm32-qspi: Remove CR_FTHRES_MASK usage
spi: fix ctrl->num_chipselect constraint
spi: spi-synquacer: Fixed build on architectures missing readsl/writesl series
spi/acpi: fix incorrect ACPI parent check
spi: don't open code list_for_each_entry_safe_reverse()
spi: No need to assign dummy value in spi_unregister_controller()
spi: Add a prototype for exported spi_set_cs_timing()
spi/acpi: enumerate all SPI slaves in the namespace
spi: qup: fix PIO/DMA transfers.
spi: Use struct_size() helper
spi: mediatek: add SPI_LSB_FIRST support
...
Diffstat (limited to 'Documentation/devicetree/bindings/mfd')
-rw-r--r-- | Documentation/devicetree/bindings/mfd/atmel-usart.txt | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/mfd/atmel-usart.txt b/Documentation/devicetree/bindings/mfd/atmel-usart.txt index 7f0cd72f47d2..699fd3c9ace8 100644 --- a/Documentation/devicetree/bindings/mfd/atmel-usart.txt +++ b/Documentation/devicetree/bindings/mfd/atmel-usart.txt @@ -17,17 +17,24 @@ Required properties for USART in SPI mode: - cs-gpios: chipselects (internal cs not supported) - atmel,usart-mode : Must be <AT91_USART_MODE_SPI> (found in dt-bindings/mfd/at91-usart.h) +Optional properties in serial and SPI mode: +- dma bindings for dma transfer: + - dmas: DMA specifier, consisting of a phandle to DMA controller node, + memory peripheral interface and USART DMA channel ID, FIFO configuration. + The order of DMA channels is fixed. The first DMA channel must be TX + associated channel and the second one must be RX associated channel. + Refer to dma.txt and atmel-dma.txt for details. + - dma-names: "tx" for TX channel. + "rx" for RX channel. + The order of dma-names is also fixed. The first name must be "tx" + and the second one must be "rx" as in the examples below. + Optional properties in serial mode: - atmel,use-dma-rx: use of PDC or DMA for receiving data - atmel,use-dma-tx: use of PDC or DMA for transmitting data - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively. It will use specified PIO instead of the peripheral function pin for the USART feature. If unsure, don't specify this property. -- add dma bindings for dma transfer: - - dmas: DMA specifier, consisting of a phandle to DMA controller node, - memory peripheral interface and USART DMA channel ID, FIFO configuration. - Refer to dma.txt and atmel-dma.txt for details. - - dma-names: "rx" for RX channel, "tx" for TX channel. - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO capable USARTs. - rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt @@ -81,5 +88,8 @@ Example: interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; clocks = <&usart0_clk>; clock-names = "usart"; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; cs-gpios = <&pioB 3 0>; }; |