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| author | Christian Marangi <ansuelsmth@gmail.com> | 2024-06-20 17:26:43 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2024-06-27 10:44:29 +0200 |
| commit | 3de96d810ffd712b7ad2bd764c1390fac2436551 (patch) | |
| tree | 5f547f7ee7a3df73e4ef59c8fddd1c0cc8b73bc5 /Documentation/devicetree/bindings/mips | |
| parent | mips: bmips: rework and cache CBR addr handling (diff) | |
| download | linux-3de96d810ffd712b7ad2bd764c1390fac2436551.tar.xz linux-3de96d810ffd712b7ad2bd764c1390fac2436551.zip | |
dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property
Document brcm,bmips-cbr-reg property.
Some SoC suffer from a BUG where CBR(Core Base Register)
address might be badly or never initialized by the Bootloader
or reading it from co-processor registers, if the system boots
from secondary CPU, results in invalid address.
The CBR address is always the same on the SoC.
Usage of this property is to give an address also in these broken
configuration/bootloader.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'Documentation/devicetree/bindings/mips')
| -rw-r--r-- | Documentation/devicetree/bindings/mips/brcm/soc.yaml | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml index 975945ca2888..0cc634482a6a 100644 --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml @@ -55,6 +55,16 @@ properties: under the "cpus" node. $ref: /schemas/types.yaml#/definitions/uint32 + brcm,bmips-cbr-reg: + description: Reference address of the CBR. + Some SoC suffer from a BUG where CBR(Core Base Register) + address might be badly or never initialized by the Bootloader + or reading it from co-processor registers, if the system boots + from secondary CPU, results in invalid address. + The CBR address is always the same on the SoC hence it + can be provided in DT to handle these broken case. + $ref: /schemas/types.yaml#/definitions/uint32 + patternProperties: "^cpu@[0-9]$": type: object @@ -64,6 +74,20 @@ properties: required: - mips-hpt-frequency +if: + properties: + compatible: + contains: + enum: + - brcm,bcm6358 + - brcm,bcm6368 + +then: + properties: + cpus: + required: + - brcm,bmips-cbr-reg + additionalProperties: true examples: |