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authorUlf Hansson <ulf.hansson@linaro.org>2017-01-25 12:44:13 +0100
committerUlf Hansson <ulf.hansson@linaro.org>2017-02-13 13:20:45 +0100
commit41efc76e0c0414d1e38a9d974a544aa80a653956 (patch)
tree68d0ce50b6da9fb07bfe3a8e42b84e1d42adb3ae /Documentation/devicetree/bindings/mmc/mmc.txt
parentmmc: core: Invent MMC_CAP_3_3V_DDR (diff)
downloadlinux-41efc76e0c0414d1e38a9d974a544aa80a653956.tar.xz
linux-41efc76e0c0414d1e38a9d974a544aa80a653956.zip
mmc: dt: Document binding for eMMC DDR 3.3V I/O voltage support
Cc: <devicetree@vger.kernel.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Tested-by: Jan Glauber <jglauber@cavium.com> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Acked-by: Rob Herring <robh@kernel.org>
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diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt
index 8a377827695b..c7f4a0ec48ed 100644
--- a/Documentation/devicetree/bindings/mmc/mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/mmc.txt
@@ -40,6 +40,7 @@ Optional properties:
- cap-mmc-hw-reset: eMMC hardware reset is supported
- cap-sdio-irq: enable SDIO IRQ signalling on this interface
- full-pwr-cycle: full power cycle of the card is supported
+- mmc-ddr-3_3v: eMMC high-speed DDR mode(3.3V I/O) is supported
- mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
- mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported
- mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported