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| author | Dinh Nguyen <dinguyen@kernel.org> | 2022-11-15 00:02:12 +0100 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2022-12-07 13:22:37 +0100 |
| commit | ccfa2466a456f70c0bab0cd0b64d6c8996141d2e (patch) | |
| tree | e68a7e07e83c206a15199beaab97fd587acf5793 /Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml | |
| parent | mmc: sdhci: Fix the SD tuning issue that the SDHCI_TRANSFER_MODE is cleared i... (diff) | |
| download | linux-ccfa2466a456f70c0bab0cd0b64d6c8996141d2e.tar.xz linux-ccfa2466a456f70c0bab0cd0b64d6c8996141d2e.zip | |
dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon"
Document the optional "altr,sysmgr-syscon" binding that is used to
access the System Manager register that controls the SDMMC clock
phase.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221114230217.202634-1-dinguyen@kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml | 32 |
1 files changed, 29 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml index ae6d6fca79e2..e1f5f26f3f1c 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys Designware Mobile Storage Host Controller Binding -allOf: - - $ref: "synopsys-dw-mshc-common.yaml#" - maintainers: - Ulf Hansson <ulf.hansson@linaro.org> @@ -38,6 +35,35 @@ properties: - const: biu - const: ciu + altr,sysmgr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the sysmgr node + - description: register offset that controls the SDMMC clock phase + - description: register shift for the smplsel(drive in) setting + description: + This property is optional. Contains the phandle to System Manager block + that contains the SDMMC clock-phase control register. The first value is + the pointer to the sysmgr, the 2nd value is the register offset for the + SDMMC clock phase register, and the 3rd value is the bit shift for the + smplsel(drive in) setting. + +allOf: + - $ref: synopsys-dw-mshc-common.yaml# + + - if: + properties: + compatible: + contains: + const: altr,socfpga-dw-mshc + then: + properties: + altr,sysmgr-syscon: true + else: + properties: + altr,sysmgr-syscon: false + required: - compatible - reg |