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author | Chen-Yu Tsai <wens@csie.org> | 2017-07-24 15:59:01 +0200 |
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committer | Ulf Hansson <ulf.hansson@linaro.org> | 2017-08-30 14:01:49 +0200 |
commit | ac98caefe18ab845f4cef6612209212c669008ce (patch) | |
tree | a0effb9857b4b1bde21ef9a2eea3b832c48b4ef3 /Documentation/devicetree/bindings/mmc | |
parent | mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode (diff) | |
download | linux-ac98caefe18ab845f4cef6612209212c669008ce.tar.xz linux-ac98caefe18ab845f4cef6612209212c669008ce.zip |
mmc: sunxi: Add support for A83T eMMC (MMC2)
The third MMC controller (MMC2) on the Allwinner A83T SoC is slightly
different. It supports a wider 8-bit bus, has a dedicated controllable
reset pin for eMMC, and a "new timing mode" which is supposed to deliver
better signals and thus better performance.
Add a compatible for this one to use the new timing mode not found in the
other controllers.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/mmc')
-rw-r--r-- | Documentation/devicetree/bindings/mmc/sunxi-mmc.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt index 7d53a799f140..63b57e2a10fb 100644 --- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt +++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt @@ -12,6 +12,7 @@ Required properties: * "allwinner,sun4i-a10-mmc" * "allwinner,sun5i-a13-mmc" * "allwinner,sun7i-a20-mmc" + * "allwinner,sun8i-a83t-emmc" * "allwinner,sun9i-a80-mmc" * "allwinner,sun50i-a64-emmc" * "allwinner,sun50i-a64-mmc" |