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author | Boris Brezillon <boris.brezillon@free-electrons.com> | 2016-04-01 14:26:35 +0200 |
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committer | Boris Brezillon <boris.brezillon@free-electrons.com> | 2016-04-19 22:04:51 +0200 |
commit | 2d472aba15ff169a30dc3661f837d8535af9b9ee (patch) | |
tree | 93e5885eccf445eb1d6fced6a93133a17dc64708 /Documentation/devicetree/bindings/mtd/nand.txt | |
parent | mtd: nand: jz4780: fixup, device structure assigned at probe (diff) | |
download | linux-2d472aba15ff169a30dc3661f837d8535af9b9ee.tar.xz linux-2d472aba15ff169a30dc3661f837d8535af9b9ee.zip |
mtd: nand: document the NAND controller/NAND chip DT representation
Standardize the NAND controller/NAND chip DT representation. Now, all new
NAND controller drivers should comply with this representation, even if
they are only supporting a single NAND chip.
Existing drivers can keep support for the old representation (where only
the NAND chip was described), but are encouraged to also support the new
one.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/mtd/nand.txt')
-rw-r--r-- | Documentation/devicetree/bindings/mtd/nand.txt | 37 |
1 files changed, 36 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt b/Documentation/devicetree/bindings/mtd/nand.txt index b53f92e252d4..a17662b1dfcb 100644 --- a/Documentation/devicetree/bindings/mtd/nand.txt +++ b/Documentation/devicetree/bindings/mtd/nand.txt @@ -1,4 +1,23 @@ -* MTD generic binding +* NAND chip and NAND controller generic binding + +NAND controller/NAND chip representation: + +The NAND controller should be represented with its own DT node, and all +NAND chips attached to this controller should be defined as children nodes +of the NAND controller. This representation should be enforced even for +simple controllers supporting only one chip. + +Mandatory NAND controller properties: +- #address-cells: depends on your controller. Should at least be 1 to + encode the CS line id. +- #size-cells: depends on your controller. Put zero unless you need a + mapping between CS lines and dedicated memory regions + +Optional NAND controller properties +- ranges: only needed if you need to define a mapping between CS lines and + memory regions + +Optional NAND chip properties: - nand-ecc-mode : String, operation mode of the NAND ecc mode. Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first", @@ -19,3 +38,19 @@ errors per {size} bytes". The interpretation of these parameters is implementation-defined, so not all implementations must support all possible combinations. However, implementations are encouraged to further specify the value(s) they support. + +Example: + + nand-controller { + #address-cells = <1>; + #size-cells = <0>; + + /* controller specific properties */ + + nand@0 { + reg = <0>; + nand-ecc-mode = "soft_bch"; + + /* controller specific properties */ + }; + }; |