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authorAriel D'Alessandro <ariel@vanguardiasur.com.ar>2015-12-07 11:57:27 +0100
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-02-08 08:04:57 +0100
commit4020d07e917854c4300092c12503a382315ea844 (patch)
treea392b3af67e056c995125fb6784893d46ee3bf53 /Documentation/devicetree/bindings/nvmem
parentmisc: c2port: use kobj_to_dev() (diff)
downloadlinux-4020d07e917854c4300092c12503a382315ea844.tar.xz
linux-4020d07e917854c4300092c12503a382315ea844.zip
DT: nvmem: Add NXP LPC18xx EEPROM memory binding documentation
Add the devicetree binding document for NXP LPC18xx EEPROM memory. Signed-off-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation/devicetree/bindings/nvmem')
-rw-r--r--Documentation/devicetree/bindings/nvmem/lpc1857-eeprom.txt28
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diff --git a/Documentation/devicetree/bindings/nvmem/lpc1857-eeprom.txt b/Documentation/devicetree/bindings/nvmem/lpc1857-eeprom.txt
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+++ b/Documentation/devicetree/bindings/nvmem/lpc1857-eeprom.txt
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+* NXP LPC18xx EEPROM memory NVMEM driver
+
+Required properties:
+ - compatible: Should be "nxp,lpc1857-eeprom"
+ - reg: Must contain an entry with the physical base address and length
+ for each entry in reg-names.
+ - reg-names: Must include the following entries.
+ - reg: EEPROM registers.
+ - mem: EEPROM address space.
+ - clocks: Must contain an entry for each entry in clock-names.
+ - clock-names: Must include the following entries.
+ - eeprom: EEPROM operating clock.
+ - resets: Should contain a reference to the reset controller asserting
+ the EEPROM in reset.
+ - interrupts: Should contain EEPROM interrupt.
+
+Example:
+
+ eeprom: eeprom@4000e000 {
+ compatible = "nxp,lpc1857-eeprom";
+ reg = <0x4000e000 0x1000>,
+ <0x20040000 0x4000>;
+ reg-names = "reg", "mem";
+ clocks = <&ccu1 CLK_CPU_EEPROM>;
+ clock-names = "eeprom";
+ resets = <&rgu 27>;
+ interrupts = <4>;
+ };