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authorLucas Stach <l.stach@pengutronix.de>2017-02-02 18:15:31 +0100
committerBjorn Helgaas <bhelgaas@google.com>2017-02-08 20:33:57 +0100
commit8ed81ec82a8c57c3a6ad69b4c4d3e4801163c256 (patch)
treec764dfcd5a0d894c3f3a9ecf625156c634aa6d3a /Documentation/devicetree/bindings/pci
parentPCI: mvebu: Handle changes to the bridge windows while enabled (diff)
downloadlinux-8ed81ec82a8c57c3a6ad69b4c4d3e4801163c256.tar.xz
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PCI: mvebu: Change delay after reset to the PCIe spec mandated 100ms
The current default of 20ms cause some devices, which are slow to initialize, to not show up during the bus scanning. Change this to the PCIe spec mandated 100ms and document this in the DT binding. From PCIe base spec rev 3.0, chapter "6.6.1. Conventional Reset": To allow components to perform internal initialization, system software must wait a specified minimum period following the end of a Conventional Reset of one or more devices before it is permitted to issue Configuration Requests to those devices. With a Downstream Port that does not support Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms before sending a Configuration Request to the device immediately below that Port. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'Documentation/devicetree/bindings/pci')
-rw-r--r--Documentation/devicetree/bindings/pci/mvebu-pci.txt3
1 files changed, 2 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
index 08c716b2c6b6..2de6f65ecfb1 100644
--- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt
+++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
@@ -78,7 +78,8 @@ and the following optional properties:
multiple lanes. If this property is not found, we assume that the
value is 0.
- reset-gpios: optional gpio to PERST#
-- reset-delay-us: delay in us to wait after reset de-assertion
+- reset-delay-us: delay in us to wait after reset de-assertion, if not
+ specified will default to 100ms, as required by the PCIe specification.
Example: