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| author | Kishon Vijay Abraham I <kishon@ti.com> | 2021-03-19 13:41:26 +0100 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2021-03-31 13:13:21 +0200 |
| commit | db7a346405dc71be0c4ad7f39dd7978d4d20dee0 (patch) | |
| tree | 0df6b2e5023d7b2f5461304662fcb704af3016d6 /Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml | |
| parent | phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callback (diff) | |
| download | linux-db7a346405dc71be0c4ad7f39dd7978d4d20dee0.tar.xz linux-db7a346405dc71be0c4ad7f39dd7978d4d20dee0.zip | |
dt-bindings: phy: phy-cadence-sierra: Add binding to model Sierra as clock provider
Add #clock-cells binding to model Sierra as clock provider and include
clock IDs for PLL_CMNLC and PLL_CMNLC1.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210319124128.13308-12-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml index d210843863df..84383e2e0b34 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml @@ -26,6 +26,9 @@ properties: '#size-cells': const: 0 + '#clock-cells': + const: 1 + resets: minItems: 1 maxItems: 2 @@ -49,12 +52,24 @@ properties: const: serdes clocks: - maxItems: 2 + minItems: 2 + maxItems: 4 clock-names: + minItems: 2 items: - const: cmn_refclk_dig_div - const: cmn_refclk1_dig_div + - const: pll0_refclk + - const: pll1_refclk + + assigned-clocks: + minItems: 1 + maxItems: 2 + + assigned-clock-parents: + minItems: 1 + maxItems: 2 cdns,autoconf: type: boolean |