Merge tag 'reset-for-4.15' of git://git.pengutronix.de/git/pza/linux into next/drivers

Pull "Reset controller changes for v4.15" from Philipp Zabel:

- add ARC AX10x support,
  merged from a separate branch that is also included in the ARC tree
- add Stratix10 support via socfpga
- unify socfpga, stm32, sunxi, and zx2967 into simple-reset driver
- add Meson GX reset level control and remove an unneeded check
- add Uniphier PXs3 and ethernet reset controls
- add MT7622 reset control dt-bindings header

* tag 'reset-for-4.15' of git://git.pengutronix.de/git/pza/linux:
  reset: zx2967: use the reset-simple driver
  reset: stm32: use the reset-simple driver
  reset: socfpga: use the reset-simple driver
  reset: sunxi: use reset-simple driver
  reset: add reset-simple to unify socfpga, stm32, sunxi, and zx2967
  reset: meson: remove unneeded check in meson_reset_reset
  reset: meson: add level reset support for GX SoC family
  reset: uniphier: add PXs3 reset data
  reset: mediatek: add reset controller dt-bindings required header for MT7622 SoC
  reset: socfpga: build the reset-socfpga for Stratix10 SOC
  reset: uniphier: add ethernet reset control support
  reset: socfpga: fix for 64-bit compilation
  ARC: reset: introduce AXS10x reset driver

2 files changed, 36 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt b/Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt
new file mode 100644
index 000000000000..32d8435a41df
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt
@@ -0,0 +1,33 @@
+Binding for the AXS10x reset controller
+
+This binding describes the ARC AXS10x boards custom IP-block which allows
+to control reset signals of selected peripherals. For example DW GMAC, etc...
+This block is controlled via memory-mapped register (AKA CREG) which
+represents up-to 32 reset lines.
+
+As of today only the following lines are used:
+ - DW GMAC - line 5
+
+This binding uses the common reset binding[1].
+
+[1] Documentation/devicetree/bindings/reset/reset.txt
+
+Required properties:
+- compatible: should be "snps,axs10x-reset".
+- reg: should always contain pair address - length: for creg reset
+  bits register.
+- #reset-cells: from common reset binding; Should always be set to 1.
+
+Example:
+	reset: reset-controller@11220 {
+		compatible = "snps,axs10x-reset";
+		#reset-cells = <1>;
+		reg = <0x11220 0x4>;
+	};
+
+Specifying reset lines connected to IP modules:
+	ethernet@.... {
+		....
+		resets = <&reset 5>;
+		....
+	};
diff --git a/Documentation/devicetree/bindings/reset/uniphier-reset.txt b/Documentation/devicetree/bindings/reset/uniphier-reset.txt
index 68a6f487c409..93efed629900 100644
--- a/Documentation/devicetree/bindings/reset/uniphier-reset.txt
+++ b/Documentation/devicetree/bindings/reset/uniphier-reset.txt
@@ -13,6 +13,7 @@ Required properties:
     "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC
     "socionext,uniphier-ld11-reset" - for LD11 SoC
     "socionext,uniphier-ld20-reset" - for LD20 SoC
+    "socionext,uniphier-pxs3-reset" - for PXs3 SoC
 - #reset-cells: should be 1.
 
 Example:
@@ -44,6 +45,7 @@ Required properties:
     "socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO)
     "socionext,uniphier-ld11-sd-reset"  - for LD11 SoC (SD)
     "socionext,uniphier-ld20-sd-reset"  - for LD20 SoC
+    "socionext,uniphier-pxs3-sd-reset"  - for PXs3 SoC
 - #reset-cells: should be 1.
 
 Example:
@@ -74,6 +76,7 @@ Required properties:
     "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC
     "socionext,uniphier-ld11-peri-reset" - for LD11 SoC
     "socionext,uniphier-ld20-peri-reset" - for LD20 SoC
+    "socionext,uniphier-pxs3-peri-reset" - for PXs3 SoC
 - #reset-cells: should be 1.
 
 Example: