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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2022-10-28 18:59:15 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-10 15:59:03 +0100 |
| commit | 57e1b873c2f54253f4c81bddb782e183ee6544ae (patch) | |
| tree | 8d986e45b57b1d9fe969a8151ebc56c2eb44af0f /Documentation/devicetree/bindings/riscv/cpus.yaml | |
| parent | dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC (diff) | |
| download | linux-57e1b873c2f54253f4c81bddb782e183ee6544ae.tar.xz linux-57e1b873c2f54253f4c81bddb782e183ee6544ae.zip | |
dt-bindings: riscv: Sort the CPU core list alphabetically
Sort the CPU cores list alphabetically for maintenance.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20221028165921.94487-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'Documentation/devicetree/bindings/riscv/cpus.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 90a7cabf58fe..ae7963e99225 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -28,17 +28,17 @@ properties: oneOf: - items: - enum: - - sifive,rocket0 + - canaan,k210 - sifive,bullet0 - sifive,e5 - sifive,e7 - sifive,e71 - - sifive,u74-mc - - sifive,u54 - - sifive,u74 + - sifive,rocket0 - sifive,u5 + - sifive,u54 - sifive,u7 - - canaan,k210 + - sifive,u74 + - sifive,u74-mc - const: riscv - items: - enum: |