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| author | Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> | 2021-09-20 15:25:59 +0200 |
|---|---|---|
| committer | Rob Herring <robh@kernel.org> | 2021-09-21 00:00:32 +0200 |
| commit | f46428f066dda4792760d2843f6b3addd0054ab7 (patch) | |
| tree | e68a5529169254c7108198060fe9bb3af854a9e5 /Documentation/devicetree/bindings/riscv/cpus.yaml | |
| parent | dt-bindings: arm,vexpress-juno: Add missing motherboard properties (diff) | |
| download | linux-f46428f066dda4792760d2843f6b3addd0054ab7.tar.xz linux-f46428f066dda4792760d2843f6b3addd0054ab7.zip | |
dt-bindings: riscv: correct e51 and u54-mc CPU bindings
All existing boards with sifive,e51 and sifive,u54-mc use it on top of
sifive,rocket0 compatible:
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: cpu@0: compatible: 'oneOf' conditional failed, one must be fixed:
['sifive,e51', 'sifive,rocket0', 'riscv'] is too long
Additional items are not allowed ('riscv' was unexpected)
Additional items are not allowed ('sifive,rocket0', 'riscv' were unexpected)
'riscv' was expected
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210920132559.151678-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/riscv/cpus.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index e534f6a7cfa1..aa5fb64d57eb 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -31,9 +31,7 @@ properties: - sifive,bullet0 - sifive,e5 - sifive,e7 - - sifive,e51 - sifive,e71 - - sifive,u54-mc - sifive,u74-mc - sifive,u54 - sifive,u74 @@ -41,6 +39,12 @@ properties: - sifive,u7 - canaan,k210 - const: riscv + - items: + - enum: + - sifive,e51 + - sifive,u54-mc + - const: sifive,rocket0 + - const: riscv - const: riscv # Simulator only description: Identifies that the hart uses the RISC-V instruction set |