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authorArnd Bergmann <arnd@arndb.de>2022-09-23 15:50:39 +0200
committerArnd Bergmann <arnd@arndb.de>2022-09-23 15:50:40 +0200
commit2b14d7da65009f68c7f31a20e411c2a8d133d825 (patch)
tree915b79bd851af19b322e85eaca5c473f96f42613 /Documentation/devicetree/bindings/soc
parentMerge tag 'tegra-for-6.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kern... (diff)
parentdt-bindings: arm: imx: update fsl.yaml for imx8dxl (diff)
downloadlinux-2b14d7da65009f68c7f31a20e411c2a8d133d825.tar.xz
linux-2b14d7da65009f68c7f31a20e411c2a8d133d825.zip
Merge tag 'imx-bindings-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX DT bindings for 6.1: - Add compatible for new boards: Kontron BL i.MX8MM OSM-S, MSC SM2S-IMX8PLUS SoM and SM2-MB-EP1 Carrier, i.MX8M Mini Gateworks GW7904 board, i.MX8DXL EVK Board. - Add add interconnect property for i.MX8MP various blk-ctrl devices. - Add i.MX8MP HDMI HDCP and HRV power domain DT IDs. - Add bindings for i.MX93 SRC and MEDIAMIX blk-ctrl. - A minor style fix on i.MX8MM clock binding header. * tag 'imx-bindings-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: dt-bindings: arm: imx: update fsl.yaml for imx8dxl dt-bindings: firmware: add missing resource IDs for imx8dxl dt-bindings: arm: Add i.MX8M Mini Gateworks GW7904 board dt-bindings: soc: add i.MX93 mediamix blk ctrl dt-bindings: soc: add i.MX93 SRC dt-bindings: mfd: syscon: Add i.MX93 blk ctrl system registers dt-bindings: arm: fsl: Add MSC SM2S-IMX8PLUS SoM and SM2-MB-EP1 Carrier dt-bindings: arm: fsl: Add Kontron BL i.MX8MM OSM-S board dt-bindings: arm: fsl: Rename compatibles for Kontron i.MX8MM SoM/board dt-bindings: soc: imx: add i.MX8MP vpu blk ctrl dt-bindings: soc: imx: add interconnect property for i.MX8MM vpu blk ctrl dt-bindings: soc: imx: drop minItems for i.MX8MM vpu blk ctrl dt-bindings: power: imx8mp-power: add HDMI HDCP/HRV dt-bindings: arm: fsl: imx6ul-kontron: Update bindings dt-bindings: clk: imx8mm: don't use multiple blank lines dt-bindings: soc: imx: add interconnect property for i.MX8MP hsio blk ctrl dt-bindings: soc: imx: add interconnect property for i.MX8MP hdmi blk ctrl dt-bindings: soc: imx: add interconnect property for i.MX8MP media blk ctrl Link: https://lore.kernel.org/r/20220918092806.2152700-1-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'Documentation/devicetree/bindings/soc')
-rw-r--r--Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml110
-rw-r--r--Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml9
-rw-r--r--Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml10
-rw-r--r--Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml14
-rw-r--r--Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml80
-rw-r--r--Documentation/devicetree/bindings/soc/imx/fsl,imx93-src.yaml96
6 files changed, 308 insertions, 11 deletions
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
index 26487daa64d9..d71bb20d4907 100644
--- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
@@ -27,25 +27,22 @@ properties:
const: 1
power-domains:
- minItems: 4
maxItems: 4
power-domain-names:
- items:
- - const: bus
- - const: g1
- - const: g2
- - const: h1
+ maxItems: 4
clocks:
- minItems: 3
maxItems: 3
clock-names:
- items:
- - const: g1
- - const: g2
- - const: h1
+ maxItems: 3
+
+ interconnects:
+ maxItems: 3
+
+ interconnect-names:
+ maxItems: 3
required:
- compatible
@@ -55,6 +52,97 @@ required:
- clocks
- clock-names
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8mm-vpu-blk-ctrl
+ then:
+ properties:
+ power-domains:
+ items:
+ - description: bus power domain
+ - description: G1 decoder power domain
+ - description: G2 decoder power domain
+ - description: H1 encoder power domain
+
+ power-domain-names:
+ items:
+ - const: bus
+ - const: g1
+ - const: g2
+ - const: h1
+
+ clocks:
+ items:
+ - description: G1 decoder clk
+ - description: G2 decoder clk
+ - description: H1 encoder clk
+
+ clock-names:
+ items:
+ - const: g1
+ - const: g2
+ - const: h1
+
+ interconnects:
+ items:
+ - description: G1 decoder interconnect
+ - description: G2 decoder interconnect
+ - description: H1 encoder power domain
+
+ interconnect-names:
+ items:
+ - const: g1
+ - const: g2
+ - const: h1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8mp-vpu-blk-ctrl
+ then:
+ properties:
+ power-domains:
+ items:
+ - description: bus power domain
+ - description: G1 decoder power domain
+ - description: G2 decoder power domain
+ - description: VC8000E encoder power domain
+
+ power-domain-names:
+ items:
+ - const: bus
+ - const: g1
+ - const: g2
+ - const: vc8000e
+
+ clocks:
+ items:
+ - description: G1 decoder clk
+ - description: G2 decoder clk
+ - description: VC8000E encoder clk
+
+ clock-names:
+ items:
+ - const: g1
+ - const: g2
+ - const: vc8000e
+
+ interconnects:
+ items:
+ - description: G1 decoder interconnect
+ - description: G2 decoder interconnect
+ - description: VC8000E encoder interconnect
+
+ interconnect-names:
+ items:
+ - const: g1
+ - const: g2
+ - const: vc8000e
+
additionalProperties: false
examples:
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
index 563e1d0e327f..1be4ce2a45e8 100644
--- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
@@ -52,6 +52,15 @@ properties:
- const: ref_266m
- const: ref_24m
+ interconnects:
+ maxItems: 3
+
+ interconnect-names:
+ items:
+ - const: hrv
+ - const: lcdif-hdmi
+ - const: hdcp
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml
index c1e29d94f40e..c29181a9745b 100644
--- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml
@@ -48,6 +48,16 @@ properties:
- const: usb
- const: pcie
+ interconnects:
+ maxItems: 4
+
+ interconnect-names:
+ items:
+ - const: noc-pcie
+ - const: usb1
+ - const: usb2
+ - const: pcie
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
index b246d8386ba4..dadb6108e321 100644
--- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
@@ -64,6 +64,20 @@ properties:
- const: isp
- const: phy
+ interconnects:
+ maxItems: 8
+
+ interconnect-names:
+ items:
+ - const: lcdif-rd
+ - const: lcdif-wr
+ - const: isi0
+ - const: isi1
+ - const: isi2
+ - const: isp0
+ - const: isp1
+ - const: dwe
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml
new file mode 100644
index 000000000000..792ebecec22d
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx93-media-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX93 Media blk-ctrl
+
+maintainers:
+ - Peng Fan <peng.fan@nxp.com>
+
+description:
+ The i.MX93 MEDIAMIX domain contains control and status registers known
+ as MEDIAMIX Block Control (MEDIAMIX BLK_CTRL). These registers include
+ clocking, reset, and miscellaneous top-level controls for peripherals
+ within the MEDIAMIX domain
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx93-media-blk-ctrl
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ maxItems: 10
+
+ clock-names:
+ items:
+ - const: apb
+ - const: axi
+ - const: nic
+ - const: disp
+ - const: cam
+ - const: pxp
+ - const: lcdif
+ - const: isi
+ - const: csi
+ - const: dsi
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx93-clock.h>
+ #include <dt-bindings/power/fsl,imx93-power.h>
+
+ media_blk_ctrl: system-controller@4ac10000 {
+ compatible = "fsl,imx93-media-blk-ctrl", "syscon";
+ reg = <0x4ac10000 0x10000>;
+ power-domains = <&mediamix>;
+ clocks = <&clk IMX93_CLK_MEDIA_APB>,
+ <&clk IMX93_CLK_MEDIA_AXI>,
+ <&clk IMX93_CLK_NIC_MEDIA_GATE>,
+ <&clk IMX93_CLK_MEDIA_DISP_PIX>,
+ <&clk IMX93_CLK_CAM_PIX>,
+ <&clk IMX93_CLK_PXP_GATE>,
+ <&clk IMX93_CLK_LCDIF_GATE>,
+ <&clk IMX93_CLK_ISI_GATE>,
+ <&clk IMX93_CLK_MIPI_CSI_GATE>,
+ <&clk IMX93_CLK_MIPI_DSI_GATE>;
+ clock-names = "apb", "axi", "nic", "disp", "cam",
+ "pxp", "lcdif", "isi", "csi", "dsi";
+ #power-domain-cells = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-src.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-src.yaml
new file mode 100644
index 000000000000..c1cc69b51981
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-src.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx93-src.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX93 System Reset Controller
+
+maintainers:
+ - Peng Fan <peng.fan@nxp.com>
+
+description: |
+ The System Reset Controller (SRC) is responsible for the generation of
+ all the system reset signals and boot argument latching.
+
+ Its main functions are as follows,
+ - Deals with all global system reset sources from other modules,
+ and generates global system reset.
+ - Responsible for power gating of MIXs (Slices) and their memory
+ low power control.
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx93-src
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ ranges: true
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+patternProperties:
+ "power-domain@[0-9a-f]+$":
+
+ type: object
+ properties:
+ compatible:
+ items:
+ - const: fsl,imx93-src-slice
+
+ '#power-domain-cells':
+ const: 0
+
+ reg:
+ items:
+ - description: mix slice register region
+ - description: mem slice register region
+
+ clocks:
+ description: |
+ A number of phandles to clocks that need to be enabled
+ during domain power-up sequencing to ensure reset
+ propagation into devices located inside this power domain.
+ minItems: 1
+ maxItems: 5
+
+ required:
+ - compatible
+ - '#power-domain-cells'
+ - reg
+
+required:
+ - compatible
+ - reg
+ - ranges
+ - '#address-cells'
+ - '#size-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx93-clock.h>
+
+ system-controller@44460000 {
+ compatible = "fsl,imx93-src", "syscon";
+ reg = <0x44460000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mediamix: power-domain@0 {
+ compatible = "fsl,imx93-src-slice";
+ reg = <0x44462400 0x400>, <0x44465800 0x400>;
+ #power-domain-cells = <0>;
+ clocks = <&clk IMX93_CLK_MEDIA_AXI>,
+ <&clk IMX93_CLK_MEDIA_APB>;
+ };
+ };