Merge tag 'spi-v5.0' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi updates from Mark Brown:
 "One new core feature here, a small collection of new drivers and a
  bunch of small improvements in existing drivers:

   - A new CS_WORD flag for transfers where the chip select is toggled
     at every word, with both a generic implementation and the ability
     for controllers to do this automatically (including a DaVinci one).

   - New drivers for Mediatek MT2712, Qualcomm GENI and QSPI, Spreadtrum
     SPI and ST STM32 QSPI plus new IDs for several existing ones"

* tag 'spi-v5.0' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (86 commits)
  spi: lpspi: add imx8qxp compatible string
  spi: Allow building SPI_BCM63XX_HSSPI on ARM-based SoCs
  spi: omap2-mcspi: Add slave mode support
  spi: omap2-mcspi: Set FIFO DMA trigger level to word length
  spi: omap2-mcspi: Switch to readl_poll_timeout()
  spi: spi-mem: add stm32 qspi controller
  dt-bindings: spi: add stm32 qspi controller
  spi: sh-msiof: document R8A779{7|8}0 bindings
  spi: pic32-sqi: don't pass GFP_DMA32 to dma_alloc_coherent
  MAINTAINERS: Add entry for Broadcom SPI controller
  spi: sh-msiof: fix deferred probing
  spi: imx: use PIO mode if size is small
  spi: imx: correct wml as the last sg length
  spi: imx: move wml setting to later than setup_transfer
  PCI: Provide pci_match_id() with CONFIG_PCI=n
  spi: Make GPIO CSs honour the SPI_NO_CS flag
  spi/spi-pxa2xx: add PXA2xx SSP SPI Controller
  spi: pxa2xx: Add devicetree support
  spi: pxa2xx: Use an enum for type
  spi: spi-geni-qcom: Add SPI driver support for GENI based QUP
  ...

1 files changed, 36 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
new file mode 100644
index 000000000000..1d64b61f5171
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
@@ -0,0 +1,36 @@
+Qualcomm Quad Serial Peripheral Interface (QSPI)
+
+The QSPI controller allows SPI protocol communication in single, dual, or quad
+wire transmission modes for read/write access to slaves such as NOR flash.
+
+Required properties:
+- compatible:	An SoC specific identifier followed by "qcom,qspi-v1", such as
+		"qcom,sdm845-qspi", "qcom,qspi-v1"
+- reg:		Should contain the base register location and length.
+- interrupts:	Interrupt number used by the controller.
+- clocks:	Should contain the core and AHB clock.
+- clock-names:	Should be "core" for core clock and "iface" for AHB clock.
+
+SPI slave nodes must be children of the SPI master node and can contain
+properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+
+	qspi: spi@88df000 {
+		compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
+		reg = <0x88df000 0x600>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "iface", "core";
+		clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+			 <&gcc GCC_QSPI_CORE_CLK>;
+
+		flash@0 {
+			compatible = "jedec,spi-nor";
+			reg = <0>;
+			spi-max-frequency = <25000000>;
+			spi-tx-bus-width = <2>;
+			spi-rx-bus-width = <2>;
+		};
+	};