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author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-07-09 18:17:59 +0200 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-07-09 18:17:59 +0200 |
commit | c6b6cebbc597aaf7d941f781b5fc114c58cc3352 (patch) | |
tree | a99ad03f0f53552338db140f34c325e47c6b54e4 /Documentation/devicetree/bindings/spi/spi-bus.txt | |
parent | Merge tag 'regulator-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/b... (diff) | |
parent | Merge remote-tracking branch 'spi/topic/pump-rt' into spi-next (diff) | |
download | linux-c6b6cebbc597aaf7d941f781b5fc114c58cc3352.tar.xz linux-c6b6cebbc597aaf7d941f781b5fc114c58cc3352.zip |
Merge tag 'spi-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown:
"For the most part this is a quiet release for SPI, though there's
several of the more widely used drivers that have had some fairly
substantial development done on them, mainly improving performance and
adding support for some more obscure use cases.
Summary:
- Support for configuring a minimum time for chip select to be
deasserted between transfers from Martin Sperl.
- A rework of the ACPI device instantiation code from Ard Biesheuvel.
- Fairly substantial development on the AT91 USART, BCM2835 and
Tegra114 drivers.
- New driver for Socionext SynQuacer"
* tag 'spi-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (58 commits)
spi: pxa2xx: Add support for Intel Elkhart Lake
spi: atmel-quadspi: fix resume call
spi: atmel-quadspi: void return type for atmel_qspi_init()
spi: pxa2xx: Set minimum transfer speed
spi: stm32-qspi: remove signal sensitive on completion
dt-bindings: spi: stm32-qspi: add dma properties
spi: uniphier: fix zero-length transfer
spi: uniphier: fix timeout error
spi/acpi: avoid spurious matches during slave enumeration
spi: spi-stm32-qspi: Remove CR_FTHRES_MASK usage
spi: fix ctrl->num_chipselect constraint
spi: spi-synquacer: Fixed build on architectures missing readsl/writesl series
spi/acpi: fix incorrect ACPI parent check
spi: don't open code list_for_each_entry_safe_reverse()
spi: No need to assign dummy value in spi_unregister_controller()
spi: Add a prototype for exported spi_set_cs_timing()
spi/acpi: enumerate all SPI slaves in the namespace
spi: qup: fix PIO/DMA transfers.
spi: Use struct_size() helper
spi: mediatek: add SPI_LSB_FIRST support
...
Diffstat (limited to 'Documentation/devicetree/bindings/spi/spi-bus.txt')
-rw-r--r-- | Documentation/devicetree/bindings/spi/spi-bus.txt | 112 |
1 files changed, 1 insertions, 111 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt index 1f6e86f787ef..e07783505498 100644 --- a/Documentation/devicetree/bindings/spi/spi-bus.txt +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt @@ -1,111 +1 @@ -SPI (Serial Peripheral Interface) busses - -SPI busses can be described with a node for the SPI controller device -and a set of child nodes for each SPI slave on the bus. The system's SPI -controller may be described for use in SPI master mode or in SPI slave mode, -but not for both at the same time. - -The SPI controller node requires the following properties: -- compatible - Name of SPI bus controller following generic names - recommended practice. - -In master mode, the SPI controller node requires the following additional -properties: -- #address-cells - number of cells required to define a chip select - address on the SPI bus. -- #size-cells - should be zero. - -In slave mode, the SPI controller node requires one additional property: -- spi-slave - Empty property. - -No other properties are required in the SPI bus node. It is assumed -that a driver for an SPI bus device will understand that it is an SPI bus. -However, the binding does not attempt to define the specific method for -assigning chip select numbers. Since SPI chip select configuration is -flexible and non-standardized, it is left out of this binding with the -assumption that board specific platform code will be used to manage -chip selects. Individual drivers can define additional properties to -support describing the chip select layout. - -Optional properties (master mode only): -- cs-gpios - gpios chip select. -- num-cs - total number of chipselects. - -If cs-gpios is used the number of chip selects will be increased automatically -with max(cs-gpios > hw cs). - -So if for example the controller has 2 CS lines, and the cs-gpios -property looks like this: - -cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>; - -Then it should be configured so that num_chipselect = 4 with the -following mapping: - -cs0 : &gpio1 0 0 -cs1 : native -cs2 : &gpio1 1 0 -cs3 : &gpio1 2 0 - - -SPI slave nodes must be children of the SPI controller node. - -In master mode, one or more slave nodes (up to the number of chip selects) can -be present. Required properties are: -- compatible - Name of SPI device following generic names recommended - practice. -- reg - Chip select address of device. -- spi-max-frequency - Maximum SPI clocking speed of device in Hz. - -In slave mode, the (single) slave node is optional. -If present, it must be called "slave". Required properties are: -- compatible - Name of SPI device following generic names recommended - practice. - -All slave nodes can contain the following optional properties: -- spi-cpol - Empty property indicating device requires inverse clock - polarity (CPOL) mode. -- spi-cpha - Empty property indicating device requires shifted clock - phase (CPHA) mode. -- spi-cs-high - Empty property indicating device requires chip select - active high. -- spi-3wire - Empty property indicating device requires 3-wire mode. -- spi-lsb-first - Empty property indicating device requires LSB first mode. -- spi-tx-bus-width - The bus width (number of data wires) that is used for MOSI. - Defaults to 1 if not present. -- spi-rx-bus-width - The bus width (number of data wires) that is used for MISO. - Defaults to 1 if not present. -- spi-rx-delay-us - Microsecond delay after a read transfer. -- spi-tx-delay-us - Microsecond delay after a write transfer. - -Some SPI controllers and devices support Dual and Quad SPI transfer mode. -It allows data in the SPI system to be transferred using 2 wires (DUAL) or 4 -wires (QUAD). -Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is -only 1 (SINGLE), 2 (DUAL) and 4 (QUAD). -Dual/Quad mode is not allowed when 3-wire mode is used. - -If a gpio chipselect is used for the SPI slave the gpio number will be passed -via the SPI master node cs-gpios property. - -SPI example for an MPC5200 SPI bus: - spi@f00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; - reg = <0xf00 0x20>; - interrupts = <2 13 0 2 14 0>; - interrupt-parent = <&mpc5200_pic>; - - ethernet-switch@0 { - compatible = "micrel,ks8995m"; - spi-max-frequency = <1000000>; - reg = <0>; - }; - - codec@1 { - compatible = "ti,tlv320aic26"; - spi-max-frequency = <100000>; - reg = <1>; - }; - }; +This file has moved to spi-controller.yaml. |