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authorAaron Brice <aaron.brice@datasoft.com>2015-04-03 22:39:30 +0200
committerMark Brown <broonie@kernel.org>2015-04-06 19:12:22 +0200
commitc1c14957afd3026dcbc2e7ca599e6d035c7d8e01 (patch)
treea60934cba8c3c5e5fda953f7d0cbdf87e718af48 /Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
parentspi: fsl-dspi: Fix clock rate scale values (diff)
downloadlinux-c1c14957afd3026dcbc2e7ca599e6d035c7d8e01.tar.xz
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spi: fsl-dspi: Add cs-sck delays
Adding fsl,spi-cs-sck-delay and fsl,spi-sck-cs-delay properties to support delays before and after starting the clock in a transfer. Signed-off-by: Aaron Brice <aaron.brice@datasoft.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt')
-rw-r--r--Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt8
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index cbbe16ed3874..70af78a9185e 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -16,6 +16,12 @@ Optional property:
in big endian mode, otherwise in native mode(same with CPU), for more
detail please see: Documentation/devicetree/bindings/regmap/regmap.txt.
+Optional SPI slave node properties:
+- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
+ select and the start of clock signal, at the start of a transfer.
+- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
+ signal and deactivating chip select, at the end of a transfer.
+
Example:
dspi0@4002c000 {
@@ -43,6 +49,8 @@ dspi0@4002c000 {
reg = <0>;
linux,modalias = "m25p80";
modal = "at26df081a";
+ fsl,spi-cs-sck-delay = <100>;
+ fsl,spi-sck-cs-delay = <50>;
};
};