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authorDavid Daney <david.daney@cavium.com>2012-08-22 21:25:07 +0200
committerJohn Crispin <blogic@openwrt.org>2012-08-22 23:46:38 +0200
commit6b52c00f2b4931c12117dc32a7cf6d5ee59f14ea (patch)
treea250907a597184ac43abc343b89e85692f456e41 /Documentation/devicetree/bindings/spi/spi-octeon.txt
parentMIPS: OCTEON: Add register definitions for SPI host hardware. (diff)
downloadlinux-6b52c00f2b4931c12117dc32a7cf6d5ee59f14ea.tar.xz
linux-6b52c00f2b4931c12117dc32a7cf6d5ee59f14ea.zip
spi: Add SPI master controller for OCTEON SOCs.
Add the driver, link it into the kbuild system and provide device tree binding documentation. Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Patchwork: http://patchwork.linux-mips.org/patch/4292/ Signed-off-by: John Crispin <blogic@openwrt.org>
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+Cavium, Inc. OCTEON SOC SPI master controller.
+
+Required properties:
+- compatible : "cavium,octeon-3010-spi"
+- reg : The register base for the controller.
+- interrupts : One interrupt, used by the controller.
+- #address-cells : <1>, as required by generic SPI binding.
+- #size-cells : <0>, also as required by generic SPI binding.
+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+ spi@1070000001000 {
+ compatible = "cavium,octeon-3010-spi";
+ reg = <0x10700 0x00001000 0x0 0x100>;
+ interrupts = <0 58>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ compatible = "st,m95256", "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ spi-cpha;
+ spi-cpol;
+
+ pagesize = <64>;
+ size = <32768>;
+ address-width = <16>;
+ };
+ };
+