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authorAlex Bee <knaerzche@gmail.com>2023-12-22 18:41:52 +0100
committerRob Herring <robh@kernel.org>2024-01-09 17:56:18 +0100
commit4ec295efef1ac4969a9667b40e1e91fa45d90c4a (patch)
treed0488e10d18f4bad349bcbe0c16ddc4fe3a858ac /Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
parentdt-bindings: arm: Add remote etm dt-binding (diff)
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dt-bindings: display: rockchip,inno-hdmi: Document RK3128 compatible
The integration for this SoC is different from the currently existing: It needs it's PHY's reference clock rate to calculate the DDC bus frequency correctly. The controller is also part of a powerdomain, so this gets added as an mandatory property for this variant. Signed-off-by: Alex Bee <knaerzche@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231222174220.55249-2-knaerzche@gmail.com Signed-off-by: Rob Herring <robh@kernel.org>
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