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authorStephen Warren <swarren@nvidia.com>2013-12-12 00:39:59 +0100
committerStephen Warren <swarren@nvidia.com>2013-12-12 00:39:59 +0100
commite9827d9be9777cf287dd1340e6e7a8526f9e0b70 (patch)
tree1b77b0cbf8237c6cee9b4b2b43dea317d2f74dce /Documentation/devicetree/bindings
parentMerge tag 'asoc-dma-v3.14' into for-3.14/dmas-resets-rework (diff)
parentclk: tegra: fix __clk_lookup() return value checks (diff)
downloadlinux-e9827d9be9777cf287dd1340e6e7a8526f9e0b70.tar.xz
linux-e9827d9be9777cf287dd1340e6e7a8526f9e0b70.zip
Merge tag 'clk-tegra-for-3.14' into for-3.14/dmas-resets-rework
Tegra clk branch for 3.14
Diffstat (limited to 'Documentation/devicetree/bindings')
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt59
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diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
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+NVIDIA Tegra124 Clock And Reset Controller
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
+for muxing and gating Tegra's clocks, and setting their rates.
+
+Required properties :
+- compatible : Should be "nvidia,tegra124-car"
+- reg : Should contain CAR registers location and length
+- clocks : Should contain phandle and clock specifiers for two clocks:
+ the 32 KHz "32k_in", and the board-specific oscillator "osc".
+- #clock-cells : Should be 1.
+ In clock consumers, this cell represents the clock ID exposed by the
+ CAR. The assignments may be found in header file
+ <dt-bindings/clock/tegra124-car.h>.
+
+Example SoC include file:
+
+/ {
+ tegra_car: clock {
+ compatible = "nvidia,tegra124-car";
+ reg = <0x60006000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ usb@c5004000 {
+ clocks = <&tegra_car TEGRA124_CLK_USB2>;
+ };
+};
+
+Example board file:
+
+/ {
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ osc: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <112400000>;
+ };
+
+ clk_32k: clock@1 {
+ compatible = "fixed-clock";
+ reg = <1>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
+ &tegra_car {
+ clocks = <&clk_32k> <&osc>;
+ };
+};