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authorMoritz Fischer <moritz.fischer@ettus.com>2015-10-17 00:42:28 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2015-10-18 06:57:16 +0200
commit908ca2dbc819f47ab3ef4d38f83e9e81c218b10d (patch)
tree0b9941c18f8f3d9618a2a11c6029f458fb6e1ef4 /Documentation/devicetree/bindings
parentver_linux: proc/modules, limit text processing to 'sed' (diff)
downloadlinux-908ca2dbc819f47ab3ef4d38f83e9e81c218b10d.tar.xz
linux-908ca2dbc819f47ab3ef4d38f83e9e81c218b10d.zip
ARM: dt: fpga: Added binding docs for Xilinx Zynq FPGA manager.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation/devicetree/bindings')
-rw-r--r--Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt19
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diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
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+Xilinx Zynq FPGA Manager
+
+Required properties:
+- compatible: should contain "xlnx,zynq-devcfg-1.0"
+- reg: base address and size for memory mapped io
+- interrupts: interrupt for the FPGA manager device
+- clocks: phandle for clocks required operation
+- clock-names: name for the clock, should be "ref_clk"
+- syscon: phandle for access to SLCR registers
+
+Example:
+ devcfg: devcfg@f8007000 {
+ compatible = "xlnx,zynq-devcfg-1.0";
+ reg = <0xf8007000 0x100>;
+ interrupts = <0 8 4>;
+ clocks = <&clkc 12>;
+ clock-names = "ref_clk";
+ syscon = <&slcr>;
+ };