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| author | Marijn Suijten <marijn.suijten@somainline.org> | 2023-07-23 18:08:43 +0200 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-07-27 15:33:44 +0200 |
| commit | 3b3e71f07d357ef0ee7cfb0edda33698036a0670 (patch) | |
| tree | b4316e558aa62ea30184911b05e0549345bbfa75 /Documentation/devicetree/bindings | |
| parent | dt-bindings: display/msm: Remove DSI1 ports from SM6350/SM6375 example (diff) | |
| download | linux-3b3e71f07d357ef0ee7cfb0edda33698036a0670.tar.xz linux-3b3e71f07d357ef0ee7cfb0edda33698036a0670.zip | |
dt-bindings: clock: qcom, dispcc-sm6125: Require GCC PLL0 DIV clock
The "gcc_disp_gpll0_div_clk_src" clock is consumed by the driver, will
be passed from DT, and should be required by the bindings.
Fixes: 8397c9c0c26b ("dt-bindings: clock: add QCOM SM6125 display clock bindings")
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Patchwork: https://patchwork.freedesktop.org/patch/548966/
Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-5-a3f287dd6c07@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml index 8a210c4c5f82..8fd29915bf2c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml @@ -29,6 +29,7 @@ properties: - description: Link clock from DP PHY - description: VCO DIV clock from DP PHY - description: AHB config clock from GCC + - description: GPLL0 div source from GCC clock-names: items: @@ -39,6 +40,7 @@ properties: - const: dp_phy_pll_link_clk - const: dp_phy_pll_vco_div_clk - const: cfg_ahb_clk + - const: gcc_disp_gpll0_div_clk_src '#clock-cells': const: 1 @@ -72,14 +74,16 @@ examples: <&dsi1_phy 1>, <&dp_phy 0>, <&dp_phy 1>, - <&gcc GCC_DISP_AHB_CLK>; + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; clock-names = "bi_tcxo", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk", "dsi1_phy_pll_out_dsiclk", "dp_phy_pll_link_clk", "dp_phy_pll_vco_div_clk", - "cfg_ahb_clk"; + "cfg_ahb_clk", + "gcc_disp_gpll0_div_clk_src"; #clock-cells = <1>; #power-domain-cells = <1>; }; |