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| author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2015-06-09 18:47:19 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2015-06-10 14:11:50 +0200 |
| commit | b19bf379767943f0c094490c52f3d75f9397b503 (patch) | |
| tree | 1357dffd8b9693ba1dffc9f2c23c173df63a8820 /Documentation/devicetree/bindings | |
| parent | pinctrl: mvebu: armada-xp: add nand rb function (diff) | |
| download | linux-b19bf379767943f0c094490c52f3d75f9397b503.tar.xz linux-b19bf379767943f0c094490c52f3d75f9397b503.zip | |
pinctrl: mvebu: armada-xp: add dram functions
The latest Armada XP datasheet documents several new DRAM related
functions on various MPPs. This commit adds the description of these
new functions in the Armada XP pinctrl driver and its DT binding
documentation.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings')
| -rw-r--r-- | Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index bd8af477cd4a..76da7222ff92 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -51,8 +51,8 @@ mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk) mpp30 30 gpio, tdm(int1), sd0(clk) mpp31 31 gpio, tdm(int2), sd0(cmd) mpp32 32 gpio, tdm(int3), sd0(d0) -mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat) -mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt) +mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat), dram(vttctrl) +mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt), dram(deccerr) mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) mpp36 36 gpio, spi0(mosi) mpp37 37 gpio, spi0(miso) @@ -68,7 +68,7 @@ mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout), mpp44 44 gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2), dram(bat), spi1(cs4) mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt), - spi1(cs5) + spi1(cs5), dram(vttctrl) mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt), spi1(cs6) mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3), |