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| author | Ludovic Barre <ludovic.barre@st.com> | 2017-04-13 19:15:56 +0200 |
|---|---|---|
| committer | Brian Norris <computersforpeace@gmail.com> | 2017-05-02 03:08:03 +0200 |
| commit | 4ca41cb2ae09bfd9f84f053b8b9966e1bb8accc4 (patch) | |
| tree | 854294ca297787a04edf086e464117d5ce6663b3 /Documentation/devicetree | |
| parent | Merge tag 'spi-nor/for-4.12-v2' of git://github.com/spi-nor/linux into MTD (diff) | |
| download | linux-4ca41cb2ae09bfd9f84f053b8b9966e1bb8accc4.tar.xz linux-4ca41cb2ae09bfd9f84f053b8b9966e1bb8accc4.zip | |
dt-bindings: mtd: Document the STM32 QSPI bindings
This patch adds documentation of device tree bindings for the STM32
QSPI controller.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/mtd/stm32-quadspi.txt | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt new file mode 100644 index 000000000000..ddd18c135148 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt @@ -0,0 +1,43 @@ +* STMicroelectronics Quad Serial Peripheral Interface(QuadSPI) + +Required properties: +- compatible: should be "st,stm32f469-qspi" +- reg: the first contains the register location and length. + the second contains the memory mapping address and length +- reg-names: should contain the reg names "qspi" "qspi_mm" +- interrupts: should contain the interrupt for the device +- clocks: the phandle of the clock needed by the QSPI controller +- A pinctrl must be defined to set pins in mode of operation for QSPI transfer + +Optional properties: +- resets: must contain the phandle to the reset controller. + +A spi flash must be a child of the nor_flash node and could have some +properties. Also see jedec,spi-nor.txt. + +Required properties: +- reg: chip-Select number (QSPI controller may connect 2 nor flashes) +- spi-max-frequency: max frequency of spi bus + +Optional property: +- spi-rx-bus-width: see ../spi/spi-bus.txt for the description + +Example: + +qspi: spi@a0001000 { + compatible = "st,stm32f469-qspi"; + reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = <91>; + resets = <&rcc STM32F4_AHB3_RESET(QSPI)>; + clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0>; + + flash@0 { + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + ... + }; +}; |