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| author | Anson Huang <anson.huang@nxp.com> | 2019-03-12 03:24:08 +0100 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2019-03-21 06:49:53 +0100 |
| commit | 8677858da6b9d1afc49b5ba8bfefea92e9416cd2 (patch) | |
| tree | 6327e1f1c4c06bb7293b966ce45c35299e8b95d3 /Documentation/devicetree | |
| parent | of: Add vendor prefix for Menlo Systems GmbH (diff) | |
| download | linux-8677858da6b9d1afc49b5ba8bfefea92e9416cd2.tar.xz linux-8677858da6b9d1afc49b5ba8bfefea92e9416cd2.zip | |
dt-bindings: memory-controllers: freescale: add MMDC binding doc
Freescale MMDC (Multi Mode DDR Controller) driver is supported
since i.MX6Q, but not yet documented, this patch adds binding
doc for MMDC module driver.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt new file mode 100644 index 000000000000..bcc36c5b543c --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt @@ -0,0 +1,35 @@ +Freescale Multi Mode DDR controller (MMDC) + +Required properties : +- compatible : should be one of following: + for i.MX6Q/i.MX6DL: + - "fsl,imx6q-mmdc"; + for i.MX6QP: + - "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc"; + for i.MX6SL: + - "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; + for i.MX6SLL: + - "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; + for i.MX6SX: + - "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; + for i.MX6UL/i.MX6ULL/i.MX6ULZ: + - "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; + for i.MX7ULP: + - "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc"; +- reg : address and size of MMDC DDR controller registers + +Optional properties : +- clocks : the clock provided by the SoC to access the MMDC registers + +Example : + mmdc0: memory-controller@21b0000 { /* MMDC0 */ + compatible = "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; + }; + + mmdc1: memory-controller@21b4000 { /* MMDC1 */ + compatible = "fsl,imx6q-mmdc"; + reg = <0x021b4000 0x4000>; + status = "disabled"; + }; |