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| author | Ralf Baechle <ralf@linux-mips.org> | 2012-10-05 15:56:28 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-10-05 15:56:28 +0200 |
| commit | 382fc33b4a04e2dde89b4c69a6880e0c7d9761e2 (patch) | |
| tree | 9d13ef333c4e841756c45bf29600ceac28e3f85e /Documentation/devicetree | |
| parent | MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs (diff) | |
| parent | MIPS: BCM63XX: remove bogus ENETSW_TXDMA interrupts from BCM6328 (diff) | |
| download | linux-382fc33b4a04e2dde89b4c69a6880e0c7d9761e2.tar.xz linux-382fc33b4a04e2dde89b4c69a6880e0c7d9761e2.zip | |
Merge branch 'master' of git://dev.phrozen.org/mips-next into mips-for-linux-next
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/spi/spi-octeon.txt | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-octeon.txt b/Documentation/devicetree/bindings/spi/spi-octeon.txt new file mode 100644 index 000000000000..431add192342 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-octeon.txt @@ -0,0 +1,33 @@ +Cavium, Inc. OCTEON SOC SPI master controller. + +Required properties: +- compatible : "cavium,octeon-3010-spi" +- reg : The register base for the controller. +- interrupts : One interrupt, used by the controller. +- #address-cells : <1>, as required by generic SPI binding. +- #size-cells : <0>, also as required by generic SPI binding. + +Child nodes as per the generic SPI binding. + +Example: + + spi@1070000001000 { + compatible = "cavium,octeon-3010-spi"; + reg = <0x10700 0x00001000 0x0 0x100>; + interrupts = <0 58>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "st,m95256", "atmel,at25"; + reg = <0>; + spi-max-frequency = <5000000>; + spi-cpha; + spi-cpol; + + pagesize = <64>; + size = <32768>; + address-width = <16>; + }; + }; + |