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authorDaniel Mack <zonque@gmail.com>2012-12-10 10:30:04 +0100
committerMark Brown <broonie@opensource.wolfsonmicro.com>2012-12-24 16:53:28 +0100
commitfd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3 (patch)
treea1033cbc88a3ccba164e8d0f6c7469f9efd6713a /Documentation/devicetree
parentMerge branch 'asoc-fix-cs4271' into asoc-cs4271 (diff)
downloadlinux-fd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3.tar.xz
linux-fd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3.zip
ALSA: ASoC: cs4271: add optional soft reset workaround
The CS4271 requires its LRCLK and MCLK to be stable before its RESET line is de-asserted. That also means that clocks cannot be changed without putting the chip back into hardware reset, which also requires a complete re-initialization of all registers. One (undocumented) workaround is to assert and de-assert the PDN bit in the MODE2 register. This patch adds a new flag to both the DT bindings as well as to the platform data to enable that workaround. Signed-off-by: Daniel Mack <zonque@gmail.com> Acked-by: Alexander Sverdlin <subaparts@yandex.ru> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/sound/cs4271.txt12
1 files changed, 12 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/sound/cs4271.txt b/Documentation/devicetree/bindings/sound/cs4271.txt
index a850fb9c88ea..e2cd1d7539e5 100644
--- a/Documentation/devicetree/bindings/sound/cs4271.txt
+++ b/Documentation/devicetree/bindings/sound/cs4271.txt
@@ -20,6 +20,18 @@ Optional properties:
!RESET pin
- cirrus,amuteb-eq-bmutec: When given, the Codec's AMUTEB=BMUTEC flag
is enabled.
+ - cirrus,enable-soft-reset:
+ The CS4271 requires its LRCLK and MCLK to be stable before its RESET
+ line is de-asserted. That also means that clocks cannot be changed
+ without putting the chip back into hardware reset, which also requires
+ a complete re-initialization of all registers.
+
+ One (undocumented) workaround is to assert and de-assert the PDN bit
+ in the MODE2 register. This workaround can be enabled with this DT
+ property.
+
+ Note that this is not needed in case the clocks are stable
+ throughout the entire runtime of the codec.
Examples: