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authorVinod Koul <vinod.koul@intel.com>2018-04-10 05:25:58 +0200
committerVinod Koul <vinod.koul@intel.com>2018-04-10 05:25:58 +0200
commit2ffb850e23a943acfbeda62599397c863cdd854c (patch)
tree8745a5531ed800d0788d3314ff2a5d0221cf4f8f /Documentation/devicetree
parentMerge branch 'topic/renesas' into for-linus (diff)
parentdmaengine: stm32-dma: properly mask irq bits (diff)
downloadlinux-2ffb850e23a943acfbeda62599397c863cdd854c.tar.xz
linux-2ffb850e23a943acfbeda62599397c863cdd854c.zip
Merge branch 'topic/stm' into for-linus
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/dma/stm32-dma.txt6
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/dma/stm32-dma.txt b/Documentation/devicetree/bindings/dma/stm32-dma.txt
index 0b55718bf889..c5f519097204 100644
--- a/Documentation/devicetree/bindings/dma/stm32-dma.txt
+++ b/Documentation/devicetree/bindings/dma/stm32-dma.txt
@@ -62,14 +62,14 @@ channel: a phandle to the DMA controller plus the following four integer cells:
0x1: medium
0x2: high
0x3: very high
-4. A 32bit mask specifying the DMA FIFO threshold configuration which are device
- dependent:
- -bit 0-1: Fifo threshold
+4. A 32bit bitfield value specifying DMA features which are device dependent:
+ -bit 0-1: DMA FIFO threshold selection
0x0: 1/4 full FIFO
0x1: 1/2 full FIFO
0x2: 3/4 full FIFO
0x3: full FIFO
+
Example:
usart1: serial@40011000 {