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authorKai Chieh Chuang <kaichieh.chuang@mediatek.com>2018-04-25 09:25:22 +0200
committerMark Brown <broonie@kernel.org>2018-04-25 19:52:02 +0200
commit22d9f80904b4510296c133db15f8d3291292023b (patch)
tree4542b04212559e73972fbc37768c697aeb83c792 /Documentation/devicetree
parentASoC: mt6797: add mt6797 platform driver (diff)
downloadlinux-22d9f80904b4510296c133db15f8d3291292023b.tar.xz
linux-22d9f80904b4510296c133db15f8d3291292023b.zip
ASoC: mediatek: add documents for mt6797
Signed-off-by: KaiChieh Chuang <kaichieh.chuang@mediatek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/sound/mt6797-afe-pcm.txt42
-rw-r--r--Documentation/devicetree/bindings/sound/mt6797-mt6351.txt14
2 files changed, 56 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/sound/mt6797-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt6797-afe-pcm.txt
new file mode 100644
index 000000000000..0ae29de15bfd
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/mt6797-afe-pcm.txt
@@ -0,0 +1,42 @@
+Mediatek AFE PCM controller for mt6797
+
+Required properties:
+- compatible = "mediatek,mt6797-audio";
+- reg: register location and size
+- interrupts: should contain AFE interrupt
+- power-domains: should define the power domain
+- clocks: Must contain an entry for each entry in clock-names
+- clock-names: should have these clock names:
+ "infra_sys_audio_clk",
+ "infra_sys_audio_26m",
+ "mtkaif_26m_clk",
+ "top_mux_audio",
+ "top_mux_aud_intbus",
+ "top_sys_pll3_d4",
+ "top_sys_pll1_d4",
+ "top_clk26m_clk";
+
+Example:
+
+ afe: mt6797-afe-pcm@11220000 {
+ compatible = "mediatek,mt6797-audio";
+ reg = <0 0x11220000 0 0x1000>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT6797_POWER_DOMAIN_AUDIO>;
+ clocks = <&infrasys CLK_INFRA_AUDIO>,
+ <&infrasys CLK_INFRA_AUDIO_26M>,
+ <&infrasys CLK_INFRA_AUDIO_26M_PAD_TOP>,
+ <&topckgen CLK_TOP_MUX_AUDIO>,
+ <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
+ <&topckgen CLK_TOP_SYSPLL3_D4>,
+ <&topckgen CLK_TOP_SYSPLL1_D4>,
+ <&clk26m>;
+ clock-names = "infra_sys_audio_clk",
+ "infra_sys_audio_26m",
+ "mtkaif_26m_clk",
+ "top_mux_audio",
+ "top_mux_aud_intbus",
+ "top_sys_pll3_d4",
+ "top_sys_pll1_d4",
+ "top_clk26m_clk";
+ };
diff --git a/Documentation/devicetree/bindings/sound/mt6797-mt6351.txt b/Documentation/devicetree/bindings/sound/mt6797-mt6351.txt
new file mode 100644
index 000000000000..1d95a8840f19
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/mt6797-mt6351.txt
@@ -0,0 +1,14 @@
+MT6797 with MT6351 CODEC
+
+Required properties:
+- compatible: "mediatek,mt6797-mt6351-sound"
+- mediatek,platform: the phandle of MT6797 ASoC platform
+- mediatek,audio-codec: the phandles of MT6351 codec
+
+Example:
+
+ sound {
+ compatible = "mediatek,mt6797-mt6351-sound";
+ mediatek,audio-codec = <&mt6351_snd>;
+ mediatek,platform = <&afe>;
+ };