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authorJisheng Zhang <jszhang@marvell.com>2016-01-20 12:27:23 +0100
committerDavid S. Miller <davem@davemloft.net>2016-01-21 21:04:59 +0100
commit2804ba4edef5b4de01d4c580eb9ab4000f822a53 (patch)
tree9c3bc5665b69bc0ac82b19b98f19066239eb8d2f /Documentation/hwmon/max16065
parentnet: mvneta: sort the headers in alphabetic order (diff)
downloadlinux-2804ba4edef5b4de01d4c580eb9ab4000f822a53.tar.xz
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net: mvneta: Try to get named core clock first
Some platforms may provide more than one clk for the mvneta IP, for example Marvell BG4CT provides one clk for the mac core, and one clk for the AXI bus logic. To support for more than one clock, we'll need to distinguish between the clock by name. Change clock probing to first try to get "core" clock before falling back to unnamed clock. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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