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| author | Chen-Yu Tsai <wens@csie.org> | 2017-07-24 15:59:01 +0200 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2017-08-30 14:01:49 +0200 |
| commit | ac98caefe18ab845f4cef6612209212c669008ce (patch) | |
| tree | a0effb9857b4b1bde21ef9a2eea3b832c48b4ef3 /Documentation/lsm.txt | |
| parent | mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode (diff) | |
| download | linux-ac98caefe18ab845f4cef6612209212c669008ce.tar.xz linux-ac98caefe18ab845f4cef6612209212c669008ce.zip | |
mmc: sunxi: Add support for A83T eMMC (MMC2)
The third MMC controller (MMC2) on the Allwinner A83T SoC is slightly
different. It supports a wider 8-bit bus, has a dedicated controllable
reset pin for eMMC, and a "new timing mode" which is supposed to deliver
better signals and thus better performance.
Add a compatible for this one to use the new timing mode not found in the
other controllers.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'Documentation/lsm.txt')
0 files changed, 0 insertions, 0 deletions