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| author | Todor Tomov <todor.tomov@linaro.org> | 2017-08-18 10:16:33 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@s-opensource.com> | 2017-08-26 21:32:10 +0200 |
| commit | 55e6efe0d6379c179045081ef527c048f855053d (patch) | |
| tree | 5a5e1d65b556f7db6a20b8cfe9443cf4267d92d6 /Documentation/media/v4l-drivers | |
| parent | media: doc: media/v4l-drivers: Qualcomm Camera Subsystem - Media graph (diff) | |
| download | linux-55e6efe0d6379c179045081ef527c048f855053d.tar.xz linux-55e6efe0d6379c179045081ef527c048f855053d.zip | |
media: doc: media/v4l-drivers/qcom_camss: Add abbreviations explanation
Add explanations for VFE's PIX and RDI interfaces.
Signed-off-by: Todor Tomov <todor.tomov@linaro.org>
Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
Diffstat (limited to 'Documentation/media/v4l-drivers')
| -rw-r--r-- | Documentation/media/v4l-drivers/qcom_camss.rst | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/Documentation/media/v4l-drivers/qcom_camss.rst b/Documentation/media/v4l-drivers/qcom_camss.rst index 7ef632a42cb6..9e66b7b5770f 100644 --- a/Documentation/media/v4l-drivers/qcom_camss.rst +++ b/Documentation/media/v4l-drivers/qcom_camss.rst @@ -34,11 +34,12 @@ driver consists of: - ISPIF (ISP Interface) module. Handles the routing of the data streams from the CSIDs to the inputs of the VFE; - VFE (Video Front End) module. Contains a pipeline of image processing hardware - blocks. The VFE has different input interfaces. The PIX input interface feeds - the input data to the image processing pipeline. The image processing pipeline - contains also a scale and crop module at the end. Three RDI input interfaces - bypass the image processing pipeline. The VFE also contains the AXI bus - interface which writes the output data to memory. + blocks. The VFE has different input interfaces. The PIX (Pixel) input + interface feeds the input data to the image processing pipeline. The image + processing pipeline contains also a scale and crop module at the end. Three + RDI (Raw Dump Interface) input interfaces bypass the image processing + pipeline. The VFE also contains the AXI bus interface which writes the output + data to memory. Supported functionality |