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| author | Paul E. McKenney <paulmck@linux.vnet.ibm.com> | 2016-01-26 07:12:34 +0100 |
|---|---|---|
| committer | Paul E. McKenney <paulmck@linux.vnet.ibm.com> | 2016-03-14 23:52:18 +0100 |
| commit | 37ef0341ca60b364dde05239c98b15c999195d8c (patch) | |
| tree | d9c46207ff501a55eec5f5f515f56251b9f9916b /Documentation/memory-barriers.txt | |
| parent | documentation: Distinguish between local and global transitivity (diff) | |
| download | linux-37ef0341ca60b364dde05239c98b15c999195d8c.tar.xz linux-37ef0341ca60b364dde05239c98b15c999195d8c.zip | |
documentation: Add alternative release-acquire outcome
The memory-barriers.txt discussion of local transitivity and
release-acquire chains leaves out discussion of the outcome of
the read from "u". This commit therefore adds an outcome showing
that you can get a "1" from this read even if the release-acquire
pairs don't line up.
Reported-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Diffstat (limited to 'Documentation/memory-barriers.txt')
| -rw-r--r-- | Documentation/memory-barriers.txt | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index ae9d306725ba..57e4a4b053c5 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -1372,6 +1372,10 @@ is possible: r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0 +As an aside, the following outcome is also possible: + + r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0 && r5 == 1 + Although cpu0(), cpu1(), and cpu2() will see their respective reads and writes in order, CPUs not involved in the release-acquire chain might well disagree on the order. This disagreement stems from the fact that |