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authorConor Dooley <conor.dooley@microchip.com>2023-12-08 17:06:51 +0100
committerPalmer Dabbelt <palmer@rivosinc.com>2024-01-11 16:36:29 +0100
commit07df87c0f8815898cb994408c4b6dd542a1394b8 (patch)
treeef5baf3fe879f9916e78673658daed490250de4f /Documentation/netlink/specs/ovs_flow.yaml
parentdt-bindings: riscv: cpus: Clarify mmu-type interpretation (diff)
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dt-bindings: riscv: permit numbers in "riscv,isa"
There are some extensions that contain numbers, such as Zve32f, which are enabled by the "max" cpu type in QEMU. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231208-uncolored-oxidant-5ab37dd3ab84@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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