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author | Conor Dooley <conor.dooley@microchip.com> | 2023-12-08 17:06:51 +0100 |
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committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-01-11 16:36:29 +0100 |
commit | 07df87c0f8815898cb994408c4b6dd542a1394b8 (patch) | |
tree | ef5baf3fe879f9916e78673658daed490250de4f /Documentation/netlink/specs/ovs_flow.yaml | |
parent | dt-bindings: riscv: cpus: Clarify mmu-type interpretation (diff) | |
download | linux-07df87c0f8815898cb994408c4b6dd542a1394b8.tar.xz linux-07df87c0f8815898cb994408c4b6dd542a1394b8.zip |
dt-bindings: riscv: permit numbers in "riscv,isa"
There are some extensions that contain numbers, such as Zve32f, which
are enabled by the "max" cpu type in QEMU.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231208-uncolored-oxidant-5ab37dd3ab84@spud
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'Documentation/netlink/specs/ovs_flow.yaml')
0 files changed, 0 insertions, 0 deletions