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authorPaolo Ornati <ornati@fastwebnet.it>2006-10-03 22:57:56 +0200
committerAdrian Bunk <bunk@stusta.de>2006-10-03 22:57:56 +0200
commit670e9f34ee3c7e052514c85014d2fdd99b672cdc (patch)
tree41f82a763ba6d5ca2fcb84d6a05808d095d4d051 /Documentation/spi/pxa2xx
parentFix typos in Documentation/: 'S' (diff)
downloadlinux-670e9f34ee3c7e052514c85014d2fdd99b672cdc.tar.xz
linux-670e9f34ee3c7e052514c85014d2fdd99b672cdc.zip
Documentation: remove duplicated words
Remove many duplicated words under Documentation/ and do other small cleanups. Examples: "and and" --> "and" "in in" --> "in" "the the" --> "the" "the the" --> "to the" ... Signed-off-by: Paolo Ornati <ornati@fastwebnet.it> Signed-off-by: Adrian Bunk <bunk@stusta.de>
Diffstat (limited to 'Documentation/spi/pxa2xx')
-rw-r--r--Documentation/spi/pxa2xx6
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/spi/pxa2xx b/Documentation/spi/pxa2xx
index 9c45f3df2e18..a1e0ee20f595 100644
--- a/Documentation/spi/pxa2xx
+++ b/Documentation/spi/pxa2xx
@@ -124,12 +124,12 @@ use a value of 8.
The "pxa2xx_spi_chip.timeout_microsecs" fields is used to efficiently handle
trailing bytes in the SSP receiver fifo. The correct value for this field is
dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific
-slave device. Please note the the PXA2xx SSP 1 does not support trailing byte
+slave device. Please note that the PXA2xx SSP 1 does not support trailing byte
timeouts and must busy-wait any trailing bytes.
The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting
into internal loopback mode. In this mode the SSP controller internally
-connects the SSPTX pin the the SSPRX pin. This is useful for initial setup
+connects the SSPTX pin to the SSPRX pin. This is useful for initial setup
testing.
The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific
@@ -208,7 +208,7 @@ DMA and PIO I/O Support
-----------------------
The pxa2xx_spi driver support both DMA and interrupt driven PIO message
transfers. The driver defaults to PIO mode and DMA transfers must enabled by
-setting the "enable_dma" flag in the "pxa2xx_spi_master" structure and and
+setting the "enable_dma" flag in the "pxa2xx_spi_master" structure and
ensuring that the "pxa2xx_spi_chip.dma_burst_size" field is non-zero. The DMA
mode support both coherent and stream based DMA mappings.