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author | Changbin Du <changbin.du@intel.com> | 2018-02-17 06:39:46 +0100 |
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committer | Jonathan Corbet <corbet@lwn.net> | 2018-03-07 18:26:06 +0100 |
commit | 57e5f29f04860c1d4a0b21d3e35d2cf4209cf623 (patch) | |
tree | fe99b236e9dafe311cb413dc114b97750c89522e /Documentation/trace/events-msr.rst | |
parent | trace doc: convert trace/events-nmi.txt to rst format (diff) | |
download | linux-57e5f29f04860c1d4a0b21d3e35d2cf4209cf623.tar.xz linux-57e5f29f04860c1d4a0b21d3e35d2cf4209cf623.zip |
trace doc: convert trace/events-msr.txt to rst format
This converts the plain text documentation to reStructuredText format and
add it into Sphinx TOC tree. No essential content change.
Cc: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Diffstat (limited to 'Documentation/trace/events-msr.rst')
-rw-r--r-- | Documentation/trace/events-msr.rst | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/Documentation/trace/events-msr.rst b/Documentation/trace/events-msr.rst new file mode 100644 index 000000000000..e938aa0b6f4f --- /dev/null +++ b/Documentation/trace/events-msr.rst @@ -0,0 +1,40 @@ +================ +MSR Trace Events +================ + +The x86 kernel supports tracing most MSR (Model Specific Register) accesses. +To see the definition of the MSRs on Intel systems please see the SDM +at http://www.intel.com/sdm (Volume 3) + +Available trace points: + +/sys/kernel/debug/tracing/events/msr/ + +Trace MSR reads: + +read_msr + + - msr: MSR number + - val: Value written + - failed: 1 if the access failed, otherwise 0 + + +Trace MSR writes: + +write_msr + + - msr: MSR number + - val: Value written + - failed: 1 if the access failed, otherwise 0 + + +Trace RDPMC in kernel: + +rdpmc + +The trace data can be post processed with the postprocess/decode_msr.py script:: + + cat /sys/kernel/debug/tracing/trace | decode_msr.py /usr/src/linux/include/asm/msr-index.h + +to add symbolic MSR names. + |