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author | Christoffer Dall <christoffer.dall@linaro.org> | 2013-10-25 18:29:18 +0200 |
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committer | Christoffer Dall <christoffer.dall@linaro.org> | 2013-12-21 19:01:16 +0100 |
commit | 7330672befe6269e575f79b924a7068b26c144b4 (patch) | |
tree | 1eb2d427d0be36103633b623182b65e8a3dfbf42 /Documentation/virtual | |
parent | ARM: KVM: Allow creating the VGIC after VCPUs (diff) | |
download | linux-7330672befe6269e575f79b924a7068b26c144b4.tar.xz linux-7330672befe6269e575f79b924a7068b26c144b4.zip |
KVM: arm-vgic: Support KVM_CREATE_DEVICE for VGIC
Support creating the ARM VGIC device through the KVM_CREATE_DEVICE
ioctl, which can then later be leveraged to use the
KVM_{GET/SET}_DEVICE_ATTR, which is useful both for setting addresses in
a more generic API than the ARM-specific one and is useful for
save/restore of VGIC state.
Adds KVM_CAP_DEVICE_CTRL to ARM capabilities.
Note that we change the check for creating a VGIC from bailing out if
any VCPUs were created, to bailing out if any VCPUs were ever run. This
is an important distinction that shouldn't break anything, but allows
creating the VGIC after the VCPUs have been created.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Diffstat (limited to 'Documentation/virtual')
-rw-r--r-- | Documentation/virtual/kvm/devices/arm-vgic.txt | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/virtual/kvm/devices/arm-vgic.txt b/Documentation/virtual/kvm/devices/arm-vgic.txt new file mode 100644 index 000000000000..38f27f709a99 --- /dev/null +++ b/Documentation/virtual/kvm/devices/arm-vgic.txt @@ -0,0 +1,10 @@ +ARM Virtual Generic Interrupt Controller (VGIC) +=============================================== + +Device types supported: + KVM_DEV_TYPE_ARM_VGIC_V2 ARM Generic Interrupt Controller v2.0 + +Only one VGIC instance may be instantiated through either this API or the +legacy KVM_CREATE_IRQCHIP api. The created VGIC will act as the VM interrupt +controller, requiring emulated user-space devices to inject interrupts to the +VGIC instead of directly to CPUs. |